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    Translation table and method for compressed data
    2.
    发明授权
    Translation table and method for compressed data 有权
    压缩数据的翻译表和方法

    公开(公告)号：US08954683B2

    公开(公告)日：2015-02-10

    申请号：US13587246

    申请日：2012-08-16

    Applicant: Bulent Abali ,  James A. Marcella ,  Michael Mi Tsao ,  Steven M. Wheeler

    Inventor： Bulent Abali ,  James A. Marcella ,  Michael Mi Tsao ,  Steven M. Wheeler

    IPC: G06F12/00

    CPC classification number: G06F12/10 ,  G06F12/0292 ,  G06F2212/1044 ,  G06F2212/656

    Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

    Abstract translation: 转换表具有各自包括共享位和增量位的条目，指针指向包括重用位的存储器块。 当两个转换表条目引用存储器块中的相同片段时，转换表条目中的一个被改变以引用在另一个转换表条目中引用的相同的存储器块，这释放了存储器块。 共享位被设置为指示转换表条目与另一个转换表条目共享其存储器块。 此外，转换表条目可以包括引用存储器块中不与其他转换表条目共享的存储器片段的指针形式的专用增量。 当转换表具有专用增量时，其增量位被设置。

    IMPLEMENTING EFFICIENT CACHE TAG LOOKUP IN VERY LARGE CACHE SYSTEMS
    3.
    发明申请
    IMPLEMENTING EFFICIENT CACHE TAG LOOKUP IN VERY LARGE CACHE SYSTEMS 审中-公开
    在非常大的高速缓存系统中实现高效的高速缓存标签

    公开(公告)号：US20140047175A1

    公开(公告)日：2014-02-13

    申请号：US13570778

    申请日：2012-08-09

    Applicant: Bulent Abali ,  Bruce L. Beukema ,  James A. Marcella ,  Paul G. Reuland ,  Michael M. Tsao

    Inventor： Bulent Abali ,  Bruce L. Beukema ,  James A. Marcella ,  Paul G. Reuland ,  Michael M. Tsao

    IPC: G06F12/00

    CPC classification number: G06F12/0895 ,  G06F12/0802 ,  G06F12/0897 ,  G06F12/123 ,  G06F2212/304

    Abstract: A method and circuit for implementing a cache directory and efficient cache tag lookup in very large cache systems, and a design structure on which the subject circuit resides are provided. A tag cache includes a fast partial large (LX) cache directory maintained separately on chip apart from a main LX cache directory (LXDIR) stored off chip in dynamic random access memory (DRAM) with large cache data (LXDATA). The tag cache stores most frequently accessed LXDIR tags. The tag cache contains predefined information enabling access to LXDATA directly on tag cache hit with matching address and data present in the LX cache. Only on tag cache misses the LXDIR is accessed to reach LXDATA.

    Abstract translation: 一种用于在非常大的缓存系统中实现高速缓存目录和高效缓存标签查找的方法和电路，以及提供了主题电路所在的设计结构。 标签高速缓存包括除了存储在具有大缓存数据（LXDATA）的动态随机存取存储器（DRAM）中的芯片外的主LX高速缓存目录（LXDIR）之外分开保存的快速部分大（LX）高速缓存目录。 标签缓存存储最常访问的LXDIR标签。 标签缓存包含预定义信息，可以直接在标签缓存命中上访问LXDATA，匹配地址和LX缓存中存在的数据。 只有在标签缓存未命中时才能访问LXDIR以达到LXDATA。

    DATA EYE MONITOR METHOD AND APPARATUS
    4.
    发明申请
    DATA EYE MONITOR METHOD AND APPARATUS 失效
    数据眼观察方法和装置

    公开(公告)号：US20090006730A1

    公开(公告)日：2009-01-01

    申请号：US11768810

    申请日：2007-06-26

    Applicant: Alan G. Gara ,  James A. Marcella ,  Martin Ohmacht

    Inventor： Alan G. Gara ,  James A. Marcella ,  Martin Ohmacht

    IPC: G06F12/00

    CPC classification number: G06F13/1689

    Abstract: An apparatus and method for providing a data eye monitor. The data eye monitor apparatus utilizes an inverter/latch string circuit and a set of latches to save the data eye for providing an infinite persistent data eye. In operation, incoming read data signals are adjusted in the first stage individually and latched to provide the read data to the requesting unit. The data is also simultaneously fed into a balanced XOR tree to combine the transitions of all incoming read data signals into a single signal. This signal is passed along a delay chain and tapped at constant intervals. The tap points are fed into latches, capturing the transitions at a delay element interval resolution. Using XORs, differences between adjacent taps and therefore transitions are detected. The eye is defined by segments that show no transitions over a series of samples. The eye size and position can be used to readjust the delay of incoming signals and/or to control environment parameters like voltage, clock speed and temperature.

    Abstract translation: 一种用于提供数据眼监护仪的装置和方法。 数据眼监视装置利用逆变器/锁存器串电路和一组锁存器来保存数据，以提供无限持续数据眼。 在操作中，输入的读数据信号在第一阶段被单独地调整并被锁存以将读取的数据提供给请求单元。 数据也被同时馈送到平衡XOR树中，以将所有输入的读取数据信号的转换组合成单个信号。 该信号沿着延迟链传递，并以恒定间隔敲击。 抽头点被馈送到锁存器，以延迟元件间隔分辨率捕获转换。 使用XOR，检测相邻抽头之间的差异，因此检测到转换之间的差异。 眼睛由在一系列样本上没有显示转换的片段定义。 眼睛大小和位置可用于重新调整输入信号的延迟和/或控制环境参数，如电压，时钟速度和温度。

    Physically Remote Shared Computer Memory
    5.
    发明申请
    Physically Remote Shared Computer Memory 审中-公开

    公开(公告)号：US20130166849A1

    公开(公告)日：2013-06-27

    申请号：US13525002

    申请日：2012-06-15

    Applicant: Bruce L. Beukema ,  Patrick M. Bland ,  Randolph S. Kolvick ,  James A. Marcella ,  Makoto Ono ,  Paul G. Reuland

    Inventor： Bruce L. Beukema ,  Patrick M. Bland ,  Randolph S. Kolvick ,  James A. Marcella ,  Makoto Ono ,  Paul G. Reuland

    IPC: G06F12/00

    CPC classification number: G06F15/167

    Abstract: A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory modules that are external to the plurality of computing devices, and a remote memory controller, the remote memory management module configured to partition the physically remote shared computer memory amongst a plurality of computing devices; each computing device including a computer processor and a local memory controller, the local memory controller including: a processor interface, a local memory interface, and a local interconnect interface; each remote memory controller including: a remote memory interface and a remote interconnect interface, wherein the remote memory controller is operatively coupled to the data communications interconnect via the remote interconnect interface such that the remote memory controller is coupled for data communications with the local memory controller over the data communications interconnect.

    Physically Remote Shared Computer Memory
    6.
    发明申请
    Physically Remote Shared Computer Memory 审中-公开
    物理远程共享计算机内存

    公开(公告)号：US20130166672A1

    公开(公告)日：2013-06-27

    申请号：US13334237

    申请日：2011-12-22

    Applicant: Bruce L. Beukema ,  Patrick M. Bland ,  Randolph S. Kolvick ,  James A. Marcella ,  Makoto Ono ,  Paul G. Reuland

    Inventor： Bruce L. Beukema ,  Patrick M. Bland ,  Randolph S. Kolvick ,  James A. Marcella ,  Makoto Ono ,  Paul G. Reuland

    IPC: G06F15/167

    CPC classification number: G06F15/167

    Abstract: A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory modules that are external to the plurality of computing devices, and a remote memory controller, the remote memory management module configured to partition the physically remote shared computer memory amongst a plurality of computing devices; each computing device including a computer processor and a local memory controller, the local memory controller including: a processor interface, a local memory interface, and a local interconnect interface; each remote memory controller including: a remote memory interface and a remote interconnect interface, wherein the remote memory controller is operatively coupled to the data communications interconnect via the remote interconnect interface such that the remote memory controller is coupled for data communications with the local memory controller over the data communications interconnect.

    Abstract translation: 一种具有物理上远程共享计算机存储器的计算系统，所述计算系统包括：远程存储器管理模块，多个计算设备，在所述多个计算设备外部的多个远程存储器模块以及远程存储器控制器， 远程存储器管理模块被配置为在多个计算设备之间划分物理上远程的共享计算机存储器; 每个计算设备包括计算机处理器和本地存储器控制器，所述本地存储器控制器包括：处理器接口，本地存储器接口和本地互连接口; 每个远程存储器控制器包括：远程存储器接口和远程互连接口，其中远程存储器控制器经由远程互连接口可操作地耦合到数据通信互连，使得远程存储器控制器被耦合用于与本地存储器控制器的数据通信 通过数据通信互连。

    Data eye monitor method and apparatus
    7.
    发明授权
    Data eye monitor method and apparatus 失效
    数据眼监护仪方法及装置

    公开(公告)号：US08108738B2

    公开(公告)日：2012-01-31

    申请号：US11768810

    申请日：2007-06-26

    Applicant: Alan G. Gara ,  James A. Marcella ,  Martin Ohmacht

    Inventor： Alan G. Gara ,  James A. Marcella ,  Martin Ohmacht

    IPC: G06K5/04 ,  G11B5/00 ,  G11B20/20

    CPC classification number: G06F13/1689

    Abstract: An apparatus and method for providing a data eye monitor. The data eye monitor apparatus utilizes an inverter/latch string circuit and a set of latches to save the data eye for providing an infinite persistent data eye. In operation, incoming read data signals are adjusted in the first stage individually and latched to provide the read data to the requesting unit. The data is also simultaneously fed into a balanced XOR tree to combine the transitions of all incoming read data signals into a single signal. This signal is passed along a delay chain and tapped at constant intervals. The tap points are fed into latches, capturing the transitions at a delay element interval resolution. Using XORs, differences between adjacent taps and therefore transitions are detected. The eye is defined by segments that show no transitions over a series of samples. The eye size and position can be used to readjust the delay of incoming signals and/or to control environment parameters like voltage, clock speed and temperature.

    Abstract translation: 一种用于提供数据眼监护仪的装置和方法。 数据眼监视装置利用逆变器/锁存器串电路和一组锁存器来保存数据，以提供无限持续数据眼。 在操作中，输入的读数据信号在第一阶段被单独地调整并被锁存以将读取的数据提供给请求单元。 数据也被同时馈送到平衡XOR树中，以将所有输入的读取数据信号的转换组合成单个信号。 该信号沿着延迟链传递，并以恒定间隔敲击。 抽头点被馈送到锁存器，以延迟元件间隔分辨率捕获转换。 使用XOR，检测相邻抽头之间的差异，因此检测到转换之间的差异。 眼睛由在一系列样本上没有显示转换的片段定义。 眼睛大小和位置可用于重新调整输入信号的延迟和/或控制环境参数，如电压，时钟速度和温度。

    ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT
    9.
    发明申请
    ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT 有权
    错误修正代码与芯片杀伤能力和省电增强

    公开(公告)号：US20090006899A1

    公开(公告)日：2009-01-01

    申请号：US11768559

    申请日：2007-06-26

    Applicant: Alan G. Gara ,  Dong Chen ,  Paul W. Coteus ,  William T. Flynn ,  James A. Marcella ,  Todd Takken ,  Barry M. Trager ,  Shmuel Winograd

    Inventor： Alan G. Gara ,  Dong Chen ,  Paul W. Coteus ,  William T. Flynn ,  James A. Marcella ,  Todd Takken ,  Barry M. Trager ,  Shmuel Winograd

    IPC: G06F11/26 ,  G06F11/16

    CPC classification number: G06F11/1012

    Abstract: A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.

    Abstract translation: 公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。 该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。 该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。 如果所有的综合征为零，则用户数据没有错误。 如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。 在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

    Method for generating a delta for compressed data
    10.
    发明授权
    Method for generating a delta for compressed data 有权

    公开(公告)号：US08904147B2

    公开(公告)日：2014-12-02

    申请号：US13609437

    申请日：2012-09-11

    Applicant: Bulent Abali ,  James A. Marcella

    Inventor： Bulent Abali ,  James A. Marcella

    IPC: G06F12/00

    CPC classification number: G06F12/10 ,  G06F12/023 ,  G06F2212/401 ,  H03M7/3084

    Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content.

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