公开(公告)号：US20230221956A1

公开(公告)日：2023-07-13

申请号：US17830453

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Huai-Mu WANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F9/30 ,  G06F7/544 ,  G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

CPC classification number: G06F9/3004 ,  G06F9/30036 ,  G06F9/3001 ,  G06F7/5443 ,  G11C16/3404 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US20230221882A1

公开(公告)日：2023-07-13

申请号：US17830471

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Huai-Mu WANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US20210117187A1

公开(公告)日：2021-04-22

申请号：US17026347

申请日：2020-09-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng CHANG ,  Han-Wen HU ,  Yueh-Han WU ,  Tse-Yuan WANG ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F9/30 ,  G06F7/544 ,  G06F9/345

Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.