公开(公告)号：US10332840B2

公开(公告)日：2019-06-25

申请号：US15464377

申请日：2017-03-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Kai-Chieh Hsu

IPC: H01L27/112 ,  H01L23/535 ,  H01L23/00 ,  G11C7/10 ,  G11C7/24 ,  G11C17/16

Abstract: A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages.

公开(公告)号：US20190067574A1

公开(公告)日：2019-02-28

申请号：US15690353

申请日：2017-08-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Po-Hao Tseng ,  Kai-Chieh Hsu

IPC: H01L45/00 ,  H05K3/34

CPC classification number: H01L45/1641 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0083 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H05K3/3494

Abstract: A method for treating a semiconductor structure is provided. A semiconductor structure comprising memory devices is provided. A forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.

公开(公告)号：US09959928B1

公开(公告)日：2018-05-01

申请号：US15377071

申请日：2016-12-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kai-Chieh Hsu ,  Feng-Min Lee ,  Yu-Yu Lin

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0064 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2013/0088 ,  G11C2013/0092 ,  G11C2213/79

Abstract: A method to program a programmable resistance memory cell includes performing one or more iterations until a verifying passes. The iterations include a) applying a programming pulse to the memory cell, and, b) after applying the programming pulse, verifying if the resistance of the memory cell is in a target resistance range. After an iteration of the one or more iterations in which the verifying passes, c) a stabilizing pulse with a polarity the same as the programming pulse is applied to the memory cell. After applying the stabilizing pulse, a second verifying determines if the resistance of the programmable element is in the target resistance range. Iterations comprising steps a), b), c), and d) are performed until the second verifying passes. Methods and apparatus are described to program a plurality of such cells, including applying a stabilizing pulse of the same polarity after programming.