公开(公告)号：US20180278418A1

公开(公告)日：2018-09-27

申请号：US15984685

申请日：2018-05-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Chin-Hung CHANG

IPC: H04L9/08

CPC classification number: H04L9/0866 ,  H04L9/0869 ,  H04L9/0891 ,  H04L9/0894

Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.

公开(公告)号：US20140132309A1

公开(公告)日：2014-05-15

申请号：US14158033

申请日：2014-01-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Meng CHAUNG ,  Chun-Hsiung HUNG ,  Kuen-Long CHANG ,  Ken-Hui CHEN

IPC: H03K17/14

CPC classification number: H03K17/145 ,  H03K19/00384 ,  H03K2005/00026

Abstract: An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.

公开(公告)号：US20220301609A1

公开(公告)日：2022-09-22

申请号：US17834287

申请日：2022-06-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung CHANG ,  Chia-Jung CHEN ,  Ken-Hui CHEN ,  Kuen-Long CHANG

IPC: G11C7/24 ,  H04L9/32 ,  G06F21/44

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

公开(公告)号：US20200241768A1

公开(公告)日：2020-07-30

申请号：US16259268

申请日：2019-01-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ken-Hui CHEN ,  Kuen-Long CHANG ,  Chin-Hung CHANG ,  Yu-Chen WANG

IPC: G06F3/06 ,  G06F12/14

Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

公开(公告)号：US20190198098A1

公开(公告)日：2019-06-27

申请号：US15850280

申请日：2017-12-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shang-Chi YANG ,  Chun-Yu LIAO ,  Ken-Hui CHEN

IPC: G11C13/00

Abstract: A memory device including an array of memory cells including bit lines, and biasing circuitry cells. A sense amplifier has a data line input connected to a data line, and a reference input. The controllable reference current source can be connected to the reference input of the sense amplifier. Control circuits on the device are configured to cause execution of a read operation, where the read operation includes a first phase in which the array is biased to induce leakage current on the selected bit line, and a second phase in which the array is biased to read a selected memory cell on the selected bit line. A circuit on the device is configured to sample the leakage current in the first phase, and to control the controllable reference current source during the second phase, as a function of the sampled leakage current.

公开(公告)号：US20180342302A1

公开(公告)日：2018-11-29

申请号：US15841622

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Su-Chueh LO ,  Chun-Yu LIAO

IPC: G11C16/26 ,  G11C16/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4093 ,  G06F13/40 ,  G06F12/02

Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

公开(公告)号：US20180335980A1

公开(公告)日：2018-11-22

申请号：US15890595

申请日：2018-02-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Su-Chueh LO ,  Shang-Chi YANG

IPC: G06F3/06

Abstract: A memory device includes a memory including first and second pages in first and second banks, respectively, an address decoder mapping command addresses to physical addresses. The memory device further includes circuitry configured to maintain a status indicating a most recently written page, decode received command sequences including command addresses and implementing an operation including (i) responsive to receiving a command sequence including a read command address that is pre-configured for reading data, causing the address decoder to map the read command address to one of the first and second pages selected according to the status, and (ii) responsive to receiving a second command sequence including a write command address that is pre-configured for writing data, causing the address decoder to map the write command address to one of the first and second pages selected according to the status.

公开(公告)号：US20180123808A1

公开(公告)日：2018-05-03

申请号：US15857341

申请日：2017-12-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung HUNG ,  Kuen-Long CHANG ,  Ken-Hui CHEN ,  Shih-Chang HUANG

IPC: H04L9/32 ,  H04L9/08

CPC classification number: H04L9/3278 ,  G09C1/00 ,  H04L9/0866 ,  H04L9/0869

Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip includes a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce an initial key and to store the initial key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The device can include logic to use a random number generator to generate a random number, and logic to combine the initial key and the random number to produce an enhanced key. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce the initial key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

公开(公告)号：US20170083439A1

公开(公告)日：2017-03-23

申请号：US14860744

申请日：2015-09-22

Applicant: Macronix International Co., Ltd.

Inventor： Kuen-Long CHANG ,  Su-Chuch LO ,  Chao Hsin LIN ,  Ken-Hui CHEN

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F2212/1016

Abstract: A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence.

公开(公告)号：US20230251782A1

公开(公告)日：2023-08-10

申请号：US17817711

申请日：2022-08-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chin-Hung CHANG ,  Chia-Jung CHEN ,  Ken-Hui CHEN ,  Chun-Hsiung HUNG

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0679

Abstract: A memory device and an associated control method are provided. The memory device includes a non-volatile memory array and a memory control circuit. The non-volatile memory array includes M secured memory zones. The memory control circuit is electrically connected to the non-volatile memory array. The memory control circuit provides a set of mapping information and searches a request key in the set of mapping information. The set of mapping information represents correspondences between N access keys and the M secured memory zones. The memory control circuit acquires at least one of the M secured memory zones if the request key is one of the N access keys, and performs an access command to the at least one of the M secured memory zones. M and N are positive integers.