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公开(公告)号：US20240079055A1
公开(公告)日：2024-03-07
申请号：US17929318
申请日：2022-09-02
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
CPC classification number: G11C13/0002 , H03K19/20
Abstract: An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.
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公开(公告)号：US20240021244A1
公开(公告)日：2024-01-18
申请号：US17812783
申请日：2022-07-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE , Ming-Hsiu LEE
CPC classification number: G11C13/004 , G06F7/5443
Abstract: A memory device includes a plurality of computing memory cells, each of which stores a weight value, receives an input value and generates an output value. Each of the computing memory cells includes a transistor connected to a bit line and a word line, receiving a sensing current through the bit line and receiving an input voltage through the word line. When the sensing current flows through the transistor, the computing memory cell generates a first voltage difference corresponding to the output value. The output value is equal to a product of the input value and the weight value.
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公开(公告)号：US20210151677A1
公开(公告)日：2021-05-20
申请号：US17162803
申请日：2021-01-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
IPC: H01L45/00
Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.
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公开(公告)号：US20190287251A1
公开(公告)日：2019-09-19
申请号：US15922987
申请日：2018-03-16
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
Abstract: Disclosed is a memory device including plural bit lines, plural word lines and a control circuit. The bit lines are configured to receive pixel data of an image. Each word line includes plural factor units. The factor units of each word line are configured differently according to plural factors of a filter. When processing a first area of the image by the filter, the control circuit inputs the pixel data within the first area of the image to the bit lines, and enables one of the word lines for operation. When processing a second area of the image by the filter, the control circuit maintains the pixel data within the second area overlapping the first area on the bit lines, and inputs the pixel data within the second area which doesn't overlap the first area to the bit lines, and enables another one of the word lines for operation.
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公开(公告)号：US20160260898A1
公开(公告)日：2016-09-08
申请号：US14638189
申请日：2015-03-04
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Erh-Kun LAI , Feng-Min LEE , Yu-Yu LIN
CPC classification number: H01L45/1253 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1625 , H01L45/1633
Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.
Abstract translation: 提供了一种用于制造存储器的方法。 在层间导体阵列之上形成绝缘层，并蚀刻以形成对应于阵列中的第一层间导体的第一开口，其中蚀刻停止在第一层间导体的第一顶表面处。 金属氧化物层形成在第一顶表面上。 第一层阻挡材料与第一开口的金属氧化物层和表面共形并与其接触。 随后，绝缘层被蚀刻以限定对应于阵列中的第二层间导体的第二开口，其中蚀刻停止在第二层间导体的第二顶表面处。 第二层阻挡材料与第一开口中的第一阻隔材料层共形并与其接触。 第一个开口填充有导电材料。
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Patent Agency Ranking
公开(公告)号：US20250169385A1
公开(公告)日：2025-05-22
申请号：US18631117
申请日：2024-04-10
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Feng-Min LEE , Yu-Yu LIN , Po-Hao TSENG , Ming-Hsiu LEE
Abstract: A semiconductor structure includes a gate, a channel structure, a gate insulating layer, a source, and a drain. The channel structure includes a threshold switching material, in which the channel structure includes a layered channel, a columnar channel, or a plurality of nanosheet channels. The gate insulating layer is disposed between the gate and the channel structure. The source is in direct contact with the channel structure. The drain is in direct contact with the channel structure.
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公开(公告)号：US20250149083A1
公开(公告)日：2025-05-08
申请号：US18504254
申请日：2023-11-08
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN
IPC: G11C11/4096 , G11C11/404 , G11C11/4076
Abstract: An in-memory computing (IMC) memory device comprises a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings. In programming, a first resistance state number of the balance computing memory cells is determined based on a first resistance state number of the computing memory cells of the memory string. In IMC operations, when a read voltage is applied to the computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents; the memory string currents charge a loading capacitor; a capacitor voltage of the loading capacitor is measured; and based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.
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公开(公告)号：US20240355387A1
公开(公告)日：2024-10-24
申请号：US18303726
申请日：2023-04-20
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0026 , G11C13/0061
Abstract: An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.
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公开(公告)号：US20240257873A1
公开(公告)日：2024-08-01
申请号：US18162728
申请日：2023-02-01
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Po-Hao TSENG , Yu-Hsuan LIN , Tian-Cih BO , Feng-Min LEE , Yu-Yu LIN
IPC: G11C15/04
CPC classification number: G11C15/046
Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.
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公开(公告)号：US20230253039A1
公开(公告)日：2023-08-10
申请号：US17842989
申请日：2022-06-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Yu LIN , Feng-Min LEE , Ming-Hsiu LEE
CPC classification number: G11C13/0033 , G11C13/004 , G11C13/0011 , G11C13/0069 , H01L45/085 , H01L45/1266
Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.
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