公开(公告)号：US20190289065A1

公开(公告)日：2019-09-19

申请号：US15924293

申请日：2018-03-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Ariel Shahar ,  Shahaf Shuler ,  Lion Levi

IPC: H04L29/08 ,  H04L1/16

Abstract: A method for communication includes receiving in a computer system a request from a peer computer system. Upon finding that the computer system is currently not ready to process the request, a Negative Acknowledgement (NAK) message is sent from the computer system to the peer computer system, at a sending time that is derived from a time at which the computer system is ready to process the request.

公开(公告)号：US10394747B1

公开(公告)日：2019-08-27

申请号：US15609433

申请日：2017-05-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Peter Paneah ,  Carl G. Ramey ,  Gil Moran ,  Adi Menachem ,  Christopher J. Jackson ,  Ilan Pardo ,  Ariel Shahar ,  Tzuriel Katoa

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.

公开(公告)号：US20190253362A1

公开(公告)日：2019-08-15

申请号：US15896128

申请日：2018-02-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Jacob Ruthstein ,  David Mozes ,  Dror Bohrer ,  Ariel Shahar ,  Lior Narkis ,  Noam Bloch

IPC: H04L12/851 ,  H04L12/801 ,  H04L12/26

Abstract: Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.

公开(公告)号：US10305772B2

公开(公告)日：2019-05-28

申请号：US15077945

申请日：2016-03-23

Applicant: Mellanox Technologies Ltd.

Inventor： Itay Zur ,  Noam Bloch ,  Ariel Shahar ,  Dotan Finkelstein

IPC: H04L12/26 ,  H04L12/861 ,  H04L29/08

Abstract: A method for communication includes receiving multiple work requests from a process running on a computer to transmit respective messages over a network. A single work item corresponding to the multiple work requests is submitted to a network interface controller (NIC) connected to the computer. In response to the single work item, multiple data packets carrying the respective messages are transmitted from the NIC to the network.

公开(公告)号：US20180004705A1

公开(公告)日：2018-01-04

申请号：US15196088

申请日：2016-06-29

Applicant: Mellanox Technologies Ltd.

Inventor： Adi Menachem ,  Ariel Shahar ,  Noam Bloch ,  Diego Crupnicoff ,  Michael Kagan

IPC: G06F15/173 ,  H04L29/06 ,  H04L5/00

CPC classification number: G06F15/17331 ,  G06F13/28 ,  H04L1/1614 ,  H04L1/1635 ,  H04L1/1809 ,  H04L69/16

Abstract: A method for data transfer includes transmitting a sequence of data packets, including at least a first packet and a second packet transmitted subsequently to the first packet, from a first computer over a network to a second computer in a single remote direct memory access (RDMA) data transfer transaction. Upon receipt of the second packet at the second computer without previously having received the first packet, a negative acknowledgment (NAK) packet is sent from the second computer over the network to the first computer, indicating that the first packet was not received. In response to the NAK packet, the first packet is retransmitted from the first computer to the second computer without retransmitting the second packet.

公开(公告)号：US20170068640A1

公开(公告)日：2017-03-09

申请号：US14847021

申请日：2015-09-08

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Ariel Shahar ,  Maria Lubeznov

IPC: G06F15/173 ,  H04L12/861 ,  H04L29/08

CPC classification number: G06F15/17331 ,  H04L49/15 ,  H04L49/9068 ,  H04L67/1097

Abstract: Communication apparatus includes a host interface for connection, via a host bus, to a host processor and a host memory, which is mapped to an address space of the host bus, and a network interface, configured to transmit and receive packets over a network. A local memory is configured to hold data in a memory space that is not mapped to the address space of the host bus. Packet processing circuitry, which is connected between the host interface and the network interface and is connected to the local memory, is configured to receive from the network interface a packet carrying a remote direct memory access (RDMA) request that is directed to an address in the local memory, and to service the RDMA request by accessing the data in the local memory.

Abstract translation: 通信装置包括主机接口，用于经由主机总线连接到被映射到主机总线的地址空间的主机处理器和主机存储器，以及被配置为经由网络发送和接收分组的网络接口。 本地存储器被配置为将数据保存在未映射到主机总线的地址空间的存储器空间中。 连接在主机接口和网络接口之间并连接到本地存储器的分组处理电路被配置为从网络接口接收携带指向地址的远程直接存储器访问（RDMA）请求的分组 本地内存，并通过访问本地内存中的数据来服务RDMA请求。

公开(公告)号：US20250080315A1

公开(公告)日：2025-03-06

申请号：US18950255

申请日：2024-11-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Ariel Shahar ,  Shahaf Shuler ,  Ariel Almog ,  Eitan Hirshberg ,  Natan Manevich

IPC: H04L7/00

Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.

公开(公告)号：US20250077440A1

公开(公告)日：2025-03-06

申请号：US18459047

申请日：2023-08-31

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Shahar ,  Shay Ben-Haim ,  Eyal Davidovitz ,  Oz Woller

IPC: G06F12/1009 ,  G06F12/0882

Abstract: In one embodiment, a processing device includes a memory to store a plurality of memory pages having corresponding physical memory addresses in the memory, store an active multilevel page table (MPT) mapping virtual to physical memory addresses for corresponding allocated memory pages stored in the memory, and store a floating MPT at least partially mapping virtual to physical memory addresses for corresponding spare memory pages stored in the memory, the floating and active MPT using a common mapping scheme, and a processor to receive a request to add a virtual to physical address mapping for more memory pages of the plurality of memory pages to the active MPT, and in response to receiving the request, adjoin at least part of the floating MPT to the active MPT so that the active MPT provides the virtual to physical address mapping for at least some memory pages of the spare memory pages.

公开(公告)号：US12223051B2

公开(公告)日：2025-02-11

申请号：US18349147

申请日：2023-07-09

Applicant: Mellanox Technologies, Ltd.

Inventor： Mor Hoyda Sfadia ,  Yuval Itkin ,  Ahmad Atamli ,  Ariel Shahar ,  Yaniv Strassberg ,  Itsik Levi

IPC: G06F21/57 ,  G06F8/65 ,  G06F9/445

Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

公开(公告)号：US20250030649A1

公开(公告)日：2025-01-23

申请号：US18224258

申请日：2023-07-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

IPC: H04L49/9057

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and packet processing circuitry operatively coupled to the network interface. The packet processing circuitry is configured to receive, via the network interface, a plurality of data packets associated with a message; determine, for each data packet, at least one corresponding reserved stride in a strided buffer; store each data packet in the at least one corresponding reserved stride; process the strided buffer upon storing the plurality of data packets in a corresponding plurality of reserved strides; and generate a completion notification indicating that the plurality of data packets in the strided buffer has been processed.