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公开(公告)号：US20170255559A1
公开(公告)日：2017-09-07
申请号：US15058262
申请日：2016-03-02
Applicant: Mellanox Technologies Ltd.
Inventor： Idan Burstein , Diego Crupnicoff , Shlomo Raikin , Michael Kagan
Abstract: A memory device includes a target memory, having a memory address space, and a volatile buffer memory, which is coupled to receive data written over a bus to the memory device for storage in specified addresses within the memory address space. A memory controller is configured to receive, via the bus, a flush instruction and, in response to the flush instruction, to immediately flush the data held in the buffer memory with specified addresses within the memory address space to the target memory.
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公开(公告)号：US20170093699A1
公开(公告)日：2017-03-30
申请号：US15278143
申请日：2016-09-28
Applicant: Mellanox Technologies Ltd.
Inventor： Diego Crupnicoff , Michael Kagan , Noam Bloch , Adi Menachem
IPC: H04L12/721 , H04L29/06 , H04L12/801
CPC classification number: H04L69/16 , H04L47/263 , H04L47/28 , H04L47/33 , Y02D50/10
Abstract: A method for congestion control includes receiving at a destination computer a packet transmitted on a given flow, in accordance with a predefined transport protocol, through a network by a transmitting network interface controller (NIC) of a source computer, and marked by an element in the network with a forward congestion notification. Upon receiving the marked packet in a receiving NIC of the destination computer, a congestion notification packet (CNP) indicating a flow to be throttled is immediately queued for transmission from the receiving NIC through the network to the source computer. Upon receiving the CNP in the transmitting NIC, transmission of further packets on at least the flow indicated by the CNP from the transmitting NIC to the network is immediately throttled, and an indication of the given flow is passed from the transmitting NIC to a protocol processing software stack running on the source computer.
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公开(公告)号：US09385949B2
公开(公告)日：2016-07-05
申请号：US13721052
申请日：2012-12-20
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Ilya Vershkov , Dror Goldenberg , Eitan Zahavi , Diego Crupnicoff , Marina Lipshteyn
IPC: H04L12/28 , H04L12/775 , H04J1/16 , H04L12/761
Abstract: A method for communication in a packet data network that includes at least first and second subnets interconnected by multiple routers and having respective first and second subnet managers. The method includes assigning respective local identifiers to ports for addressing of data link traffic within each subnet, such that the first subnet manager assigns the local identifiers in the first subnet, and the second subnet manager assigns the local identifiers in the second subnet. The routers are configured by transmitting and receiving control traffic between the subnet managers and the routers. Data packets are transmitted between network nodes in the first and second subnets via one or more of the configured routers under control of the subnet managers.
Abstract translation: 一种用于在分组数据网络中进行通信的方法，其包括由多个路由器互连并且具有相应的第一和第二子网管理器的至少第一和第二子网。 该方法包括将各自的本地标识符分配给用于寻址每个子网内的数据链路流量的端口，使得第一子网管理器在第一子网中分配本地标识符，并且第二子网管理器在第二子网中分配本地标识符。 通过在子网管理器和路由器之间发送和接收控制流量来配置路由器。 在子网管理器的控制下，经由一个或多个配置的路由器在第一和第二子网中的网络节点之间传送数据包。
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公开(公告)号：US20140095753A1
公开(公告)日：2014-04-03
申请号：US14033470
申请日：2013-09-22
Applicant: Mellanox Technologies Ltd.
Inventor： Diego Crupnicoff , Todd Wilde , Richard Graham , Michael Kagan
CPC classification number: G06F13/4022 , G06F12/0835 , G06F13/28 , G06F13/36 , G06F13/4068 , G06F13/4282 , G11C7/1072
Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.
Abstract translation: 用于主计算机的网络接口设备包括网络接口，被配置为向网络发送和从网络接收数据分组。 分组处理逻辑通过来自主计算机的系统存储器的直接存储器访问（DMA）经由网络接口传送和接收的数据分组传送数据。 存储器控制器包括被配置为连接到系统存储器的第一存储器接口和被配置为连接到主计算机的主机复合体的第二存储器接口。 开关逻辑将第一存储器接口交替地耦合到DMA配置中的分组处理逻辑，并以直通配置耦合到第二存储器接口。
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公开(公告)号：US12244670B2
公开(公告)日：2025-03-04
申请号：US18363005
申请日：2023-08-01
Applicant: Mellanox Technologies, Ltd.
Inventor： Liran Liss , Yamin Friedman , Michael Kagan , Diego Crupnicoff , Idan Burstein , Matty Kadosh , Tzah Oved , Dror Goldenberg , Ron Yuval Efraim , Alexander Eli Rosenbaum , Aviad Yehezkel , Rabia Loulou
IPC: H04L67/141 , G06F15/173 , H04L9/08 , H04L67/146 , H04L69/16
Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.
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Patent Agency Ranking
公开(公告)号：US20230379390A1
公开(公告)日：2023-11-23
申请号：US18363005
申请日：2023-08-01
Applicant: Mellanox Technologies, Ltd.
Inventor： Liran Liss , Yamin Friedman , Michael Kagan , Diego Crupnicoff , Idan Burstein , Matty Kadosh , Tzah Oved , Dror Goldenberg , Ron Yuval Efraim , Alexander Eli Rosenbaum , Aviad Yehezkel , Rabia Loulou
IPC: H04L67/141 , H04L9/08 , H04L69/16 , H04L67/146 , G06F15/173
CPC classification number: H04L67/141 , H04L9/0825 , H04L69/161 , H04L67/146 , G06F15/17331
Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.
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公开(公告)号：US10237376B2
公开(公告)日：2019-03-19
申请号：US15278143
申请日：2016-09-28
Applicant: Mellanox Technologies Ltd.
Inventor： Diego Crupnicoff , Michael Kagan , Noam Bloch , Adi Menachem , Idan Burstein
IPC: H04L12/801 , H04L29/06 , H04L12/825 , H04L12/841
Abstract: A method for congestion control includes receiving at a destination computer a packet transmitted on a given flow, in accordance with a predefined transport protocol, through a network by a transmitting network interface controller (NIC) of a source computer, and marked by an element in the network with a forward congestion notification. Upon receiving the marked packet in a receiving NIC of the destination computer, a congestion notification packet (CNP) indicating a flow to be throttled is immediately queued for transmission from the receiving NIC through the network to the source computer. Upon receiving the CNP in the transmitting NIC, transmission of further packets on at least the flow indicated by the CNP from the transmitting NIC to the network is immediately throttled, and an indication of the given flow is passed from the transmitting NIC to a protocol processing software stack running on the source computer.
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公开(公告)号：US09996491B2
公开(公告)日：2018-06-12
申请号：US15181436
申请日：2016-06-14
Applicant: Mellanox Technologies Ltd.
Inventor： Diego Crupnicoff , Todd Wilde , Richard Graham , Michael Kagan
CPC classification number: G06F13/4022 , G06F12/0835 , G06F13/28 , G06F13/36 , G06F13/4068 , G06F13/4282 , G11C7/1072
Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.
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公开(公告)号：US09548960B2
公开(公告)日：2017-01-17
申请号：US14046976
申请日：2013-10-06
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Zachy Haramaty , Diego Crupnicoff , Freddy Gabbay , Benny Koren , Amiad Marelli , Itamar Rabenstein , Ido Bukspan , Oded Zemer
IPC: H04L12/18 , H04L12/741 , H04L29/12
CPC classification number: H04L61/103 , H04L12/18 , H04L45/16 , H04L45/745
Abstract: A method for communication, includes routing unicast data packets among nodes in a network using respective Layer-3 addresses that are uniquely assigned to each of the nodes. Respective Layer-2 unicast addresses are assigned to the nodes in accordance with an algorithmic mapping of the respective Layer-3 addresses. The unicast data packets are forwarded within subnets of the network using the assigned Layer-2 addresses.
Abstract translation: 一种用于通信的方法，包括使用唯一地分配给每个节点的相应第3层地址在网络中的节点之间路由单播数据分组。 根据相应的第3层地址的算法映射，将相应的第2层单播地址分配给节点。 单播数据包使用分配的二层地址在网络的子网内转发。
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公开(公告)号：US20160283422A1
公开(公告)日：2016-09-29
申请号：US15181436
申请日：2016-06-14
Applicant: Mellanox Technologies Ltd.
Inventor： Diego Crupnicoff , Todd Wilde , Richard Graham , Michael Kagan
CPC classification number: G06F13/4022 , G06F12/0835 , G06F13/28 , G06F13/36 , G06F13/4068 , G06F13/4282 , G11C7/1072
Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.
Abstract translation: 用于主计算机的网络接口设备包括网络接口，被配置为向网络发送数据分组和从网络接收数据分组。 分组处理逻辑通过来自主计算机的系统存储器的直接存储器访问（DMA）经由网络接口传送和接收的数据分组传送数据。 存储器控制器包括被配置为连接到系统存储器的第一存储器接口和被配置为连接到主计算机的主机复合体的第二存储器接口。 开关逻辑将第一存储器接口交替地耦合到DMA配置中的分组处理逻辑，并以直通配置耦合到第二存储器接口。
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