公开(公告)号：US12224950B2

公开(公告)日：2025-02-11

申请号：US17979018

申请日：2022-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Gil Bloch ,  Ariel Shahar ,  Yossef Itigin

IPC: G06F15/16 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

公开(公告)号：US20250028658A1

公开(公告)日：2025-01-23

申请号：US18224262

申请日：2023-07-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

IPC: G06F13/16 ,  G06F9/54

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

公开(公告)号：US20250023668A1

公开(公告)日：2025-01-16

申请号：US18351544

申请日：2023-07-13

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Roee Moyal ,  Gil Kremer ,  Ortal Ben Moshe ,  Ariel Shahar

IPC: H04L1/1607 ,  H04L1/08 ,  H04L47/34

Abstract: In one embodiment, a first network device includes a host interface to receive messages from a host device, packet processing circuitry to send a batch of the messages to a second network device without waiting for an acknowledgement receipt from the second network device after sending each message, one message in the batch having a maximum message sequence number (MSN), receive a given acknowledgement receipt from the second network device indicating that all the messages in the batch have been received and including credit data indicating that there is no space in a receive work queue of the second network device for receiving an additional message, and send the additional message having an MSN greater than the maximum MSN to the second network device responsively to receiving the given acknowledgement receipt and based on the credit data indicating that there is no space in the receive work queue.

公开(公告)号：US20240187336A1

公开(公告)日：2024-06-06

申请号：US18414803

申请日：2024-01-17

Applicant: Mellanox Technologies, Ltd.

Inventor： Yamin Friedman ,  Idan Borshteen ,  Roee Moyal ,  Yuval Shpigelman

IPC: H04L45/24 ,  H04L45/00 ,  H04L47/122

CPC classification number: H04L45/24 ,  H04L45/38 ,  H04L47/122

Abstract: Technologies for spreading packets of transport flows across multiple network paths are described. A network controller includes a transport layer and a network layer. The transport layer includes a flow scheduler to schedule a transport flow from one of a plurality of transport flows. The network layer includes multipath logic to receive packets from the transport flow and select which path of a plurality of paths to a destination to use for the packets based on path congestion weights corresponding to the plurality of paths.

公开(公告)号：US11870590B2

公开(公告)日：2024-01-09

申请号：US17107990

申请日：2020-12-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Roee Moyal ,  Ariel Shahar ,  Noam Bloch ,  Ran Koren

IPC: H04L1/18 ,  H04L1/1829 ,  G06F15/173

CPC classification number: H04L1/1829 ,  G06F15/17331

Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.

公开(公告)号：US11476928B2

公开(公告)日：2022-10-18

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04L49/351 ,  H04L49/90 ,  H04W72/04 ,  H04W74/08

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.

公开(公告)号：US11102129B2

公开(公告)日：2021-08-24

申请号：US16559640

申请日：2019-09-04

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Noam Bloch ,  Roee Moyal ,  Ariel Shahar ,  Yamin Friedman ,  Yuval Shpigelman

IPC: H04L12/28 ,  H04L12/801 ,  H04L12/927 ,  H04L12/863 ,  H04L29/08 ,  H04L12/841

Abstract: A network adapter includes circuitry and one or more ports. The ports connect to a communication network including multiple network elements. The circuitry accesses outbound messages that are pending to be sent over the communication network to multiple remote nodes via the ports. At least some of the outbound messages request the remote nodes to send respective amounts of data back to the network adapter. Based on the amounts of data requested by the outbound messages, the circuitry forecasts a bandwidth of inbound response traffic, which is expected to traverse a selected network element in response to the outbound messages toward the network adapter, determines a schedule for transmitting the outbound messages to the remote nodes so that the forecasted bandwidth meets a bandwidth supported by the selected network element, and transmits the outbound messages to the remote nodes in accordance with the determined schedule.

公开(公告)号：US20210152484A1

公开(公告)日：2021-05-20

申请号：US16683302

申请日：2019-11-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yuval Shpigelman ,  Roee Moyal ,  Shahrazad Hleihel ,  Kobi Pines

IPC: H04L12/825 ,  H04L12/841 ,  H04L12/823

Abstract: A network adapter includes a receive (RX) pipeline, a transmit (TX) pipeline, hardware-implemented congestion-control circuitry, and a congestion-control processor. The RX pipeline is configured to receive packets from a network and process the received packets. The TX pipeline is configured to transmit packets to the network. The hardware-implemented congestion-control circuitry is configured to receive, from the TX pipeline and from the RX pipeline, Congestion-Control (CC) events derived from at least some of the packets transmitted to the network and from at least some of the packets received from the network, and to pre-process the CC events. The congestion-control processor is configured to receive the pre-processed CC events from the congestion-control circuitry, and to throttle a transmission rate of the packets transmitted to the network by the TX pipeline responsively to the pre-processed CC events.

公开(公告)号：US10572400B2

公开(公告)日：2020-02-25

申请号：US15623426

申请日：2017-06-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Finkelstein ,  Lior Narkis ,  Dror Bohrer ,  Roee Moyal

IPC: G06F13/16 ,  G06F13/36 ,  H04L12/801

Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.

公开(公告)号：US20180365176A1

公开(公告)日：2018-12-20

申请号：US15623426

申请日：2017-06-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Finkelstein ,  Lior Narkis ,  Dror Bohrer ,  Roee Moyal

IPC: G06F13/16 ,  H04L12/801 ,  G06F13/36

CPC classification number: G06F13/1642 ,  G06F13/36 ,  H04L47/34

Abstract: A packet processing device CPU, including multiple processing cores. A NIC, which is coupled to the CPU, includes at least one network port, receives a flow of incoming data packets in a sequential order from a packet communication network, and receive logic, which delivers the incoming data packets in the flow to a designated group of the cores for processing by the cores in the group, while distributing the incoming data packets to the cores in alternation among the cores in the group. In response to the incoming data packets, the cores in the group generate corresponding outgoing data packets and queue the outgoing data packets for transmission by the NIC in the sequential order of the incoming data packets. Transmit logic in the NIC transmits the outgoing data packets to the network in the sequential order via the at least one network port.