公开(公告)号：US20240015217A1

公开(公告)日：2024-01-11

申请号：US17858097

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: H04L67/1097

CPC classification number: H04L67/1097

Abstract: A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

公开(公告)号：US12224950B2

公开(公告)日：2025-02-11

申请号：US17979018

申请日：2022-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Gil Bloch ,  Ariel Shahar ,  Yossef Itigin

IPC: G06F15/16 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

公开(公告)号：US20250028658A1

公开(公告)日：2025-01-23

申请号：US18224262

申请日：2023-07-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

IPC: G06F13/16 ,  G06F9/54

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

公开(公告)号：US20240012773A1

公开(公告)日：2024-01-11

申请号：US17858102

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.

公开(公告)号：US20180183895A1

公开(公告)日：2018-06-28

申请号：US15390558

申请日：2016-12-26

Applicant: Mellanox Technologies Ltd.

Inventor： Shahaf Shuler ,  Noam Bloch ,  Yossef Itigin

IPC: H04L29/08 ,  G06F9/54

CPC classification number: H04L67/32 ,  G06F9/546 ,  G06F2209/548

Abstract: A network adapter includes a network interface and circuitry. The network interface is assigned a single network address in a communication network, and is configured to receive, from one or more other nodes over the communication network, messages that are destined for processing by multiple threads in one or more processing cores of a network node including the network adapter, but are nevertheless addressed to the single network address. The circuitry is configured to hold a distribution rule for distributing the messages among multiple Receive Queues (RQs) that are accessible by the threads, and to select for each message received via the network interface a respective RQ, by applying the distribution rule to the message.

公开(公告)号：US09742855B2

公开(公告)日：2017-08-22

申请号：US14834443

申请日：2015-08-25

Applicant: Mellanox Technologies Ltd.

Inventor： Shahaf Shuler ,  Noam Bloch ,  Ofer Hayut ,  Richard Graham ,  Ariel Shahar ,  Yossef Itigin

IPC: H04L29/08 ,  H04L29/06 ,  H04L12/861

CPC classification number: H04L67/26 ,  H04L49/9068 ,  H04L67/10 ,  H04L67/1093 ,  H04L67/1097 ,  H04L69/06

Abstract: A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.