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公开(公告)号：US20250077455A1
公开(公告)日：2025-03-06
申请号：US18951879
申请日：2024-11-19
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
Abstract: Operations include determining, based on a period of time during which a logical level of the signal line is maintained at a first logical level, that a data transfer to the memory array is being suspended, determining, while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level, and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed.
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公开(公告)号：US20250004962A1
公开(公告)日：2025-01-02
申请号：US18829713
申请日：2024-09-10
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data transfer across an interface bus to be suspended by toggling a logical level of a control pin from a first level that activates the data transfer to a second level that suspends the data transfer, and causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level.
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公开(公告)号：US11733887B2
公开(公告)日：2023-08-22
申请号：US17316956
申请日：2021-05-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luigi Pilolli , Ali Feiz Zarrin Ghalam , Guan Wang , Qiang Tang
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C16/32
Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.
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公开(公告)号：US11442877B2
公开(公告)日：2022-09-13
申请号：US16949510
申请日：2020-10-30
Applicant: Micron Technology, Inc.
Inventor： Guan Wang , Ali Feiz Zarrin Ghalam , Chin-Yu Chen , Jongin Kim
Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.
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公开(公告)号：US11367473B2
公开(公告)日：2022-06-21
申请号：US17247267
申请日：2020-12-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kaveh Shakeri , Ali Feiz Zarrin Ghalam , Qiang Tang , Eric N. Lee
Abstract: A system might include a first writing device and a second writing device. The first writing device might write first data to an array of memory cells in response to a first clock cycle of a clock signal. The write of the first data exceeds one clock cycle of the clock signal. The second writing device is in parallel with the first writing device. The second writing device might write second data to the array of memory cells in response to a second clock cycle of the clock signal. The second clock cycle follows the first clock cycle and the write of the second data exceeds one clock cycle of the clock signal.
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Patent Agency Ranking
公开(公告)号：US11336265B2
公开(公告)日：2022-05-17
申请号：US17214262
申请日：2021-03-26
Applicant: Micron Technology, Inc.
Inventor： Guan Wang , Qiang Tang , Ali Feiz Zarrin Ghalam
IPC: G06F1/10 , H03K3/017 , H04L25/06 , H03K5/156 , G11C7/22 , G11C29/02 , H04L7/00 , H04L25/02 , G06F1/04
Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
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公开(公告)号：US20220101898A1
公开(公告)日：2022-03-31
申请号：US17545888
申请日：2021-12-08
Applicant: Micron Technology, Inc.
Inventor： Agatino Massimo Maccarrone , Luigi Pilolli , Ali Feiz Zarrin Ghalam , Chin Yu Chen
Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.
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公开(公告)号：US20210263660A1
公开(公告)日：2021-08-26
申请号：US17316956
申请日：2021-05-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luigi Pilolli , Ali Feiz Zarrin Ghalam , Guan Wang , Qiang Tang
Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.
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公开(公告)号：US20200336135A1
公开(公告)日：2020-10-22
申请号：US16920315
申请日：2020-07-02
Applicant: Micron Technology, Inc.
Inventor： Guan Wang , Qiang Tang , Ali Feiz Zarrin Ghalam
IPC: H03K3/017 , G06F1/10 , H04L25/06 , H03K5/156 , G11C7/22 , G11C29/02 , H04L7/00 , H04L25/02 , G06F1/04
Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes an electrical circuit die having clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to compare a first duty cycle of a first voltage signal of the clock signal to a second duty cycle of a second voltage signal of the clock signal. Based on the comparison, the clock distortion calibration circuitry is configured to adjust a trim value associated with at least one of the first and the second duty cycles of the first and the second voltage signals, respectively, to calibrate at least one of the first and the second duty cycles and account for duty cycle distortion encountered as the clock signal propagates through a clock tree of the electrical circuit device.
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公开(公告)号：US20200176059A1
公开(公告)日：2020-06-04
申请号：US16205755
申请日：2018-11-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Luigi Pilolli , Agatino Massimo Maccarrone , Hoon Choi , Qiang Tang , Ali Feiz Zarrin Ghalam
Abstract: Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods.
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