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    Memory arrays
    13.
    发明授权
    Memory arrays 有权

    公开(公告)号：US10276230B2

    公开(公告)日：2019-04-30

    申请号：US15664140

    申请日：2017-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Kawamura ,  Scott J. Derner

    IPC: G11C11/24 ,  G11C11/4097 ,  G11C11/4094 ,  G11C7/02 ,  G11C11/408 ,  H01L27/108 ,  G11C11/4091

    Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

    APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES
    15.
    发明申请
    APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES 有权

    公开(公告)号：US20250118352A1

    公开(公告)日：2025-04-10

    申请号：US18746447

    申请日：2024-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Toby D. Robbs ,  Christopher J. Kawamura ,  Kang-Yong Kim

    IPC: G11C11/4091 ,  G11C5/06 ,  G11C11/4097

    Abstract: Single (1 T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.

    Integrated assemblies comprising digit lines configured to have shunted ends during a precharge operation
    17.
    发明授权
    Integrated assemblies comprising digit lines configured to have shunted ends during a precharge operation 有权

    公开(公告)号：US11074964B1

    公开(公告)日：2021-07-27

    申请号：US16825041

    申请日：2020-03-20

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Kawamura ,  Jiyun Li

    IPC: G11C5/10 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4091

    Abstract: Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes one or more first equalization transistors proximate the first and second regions, and includes a second equalization transistor proximate the SENSE AMPLIFIER circuitry. Some embodiments include an integrated assembly having a first digit line coupled with SENSE AMPLIFIER circuitry. The first digit line has a first region distal from the SENSE AMPLIFIER circuitry. A second digit line is coupled with the SENSE AMPLIFIER circuitry and has a second region distal from the SENSE AMPLIFIER circuitry. PRECHARGE circuitry includes an electrical connection coupling the first and second regions to one another.

    DRAM ARRAY ARCHITECTURE WITH ROW HAMMER STRESS MITIGATION
    18.
    发明申请
    DRAM ARRAY ARCHITECTURE WITH ROW HAMMER STRESS MITIGATION 有权

    公开(公告)号：US20210090636A1

    公开(公告)日：2021-03-25

    申请号：US17114404

    申请日：2020-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Christopher J. Kawamura ,  Charles L. Ingalls ,  Tae H. Kim

    IPC: G11C11/408 ,  G11C11/4076

    Abstract: An apparatus includes a plurality of main word line circuits. Each main word line circuit drives a respective global word line to one of an active state value, an intermediate voltage state, or a pre-charge state. The intermediate voltage state voltage is below the active state voltage and above the pre-charge state voltage. The memory device also includes a plurality of sub-word line drivers. Each sub-word line driver is connected to a corresponding global word line and configured to drive a respective local word line between the corresponding global word line voltage and a low voltage value. The apparatus further includes a plurality of phase drivers. Each phase driver is connected to a predetermined number of sub-word line drivers, where each of the predetermined number of sub-word line drivers connects to a different global word line.

    Memory device with bitline noise suppressing scheme
    20.
    发明授权
    Memory device with bitline noise suppressing scheme 有权

    公开(公告)号：US10861787B1

    公开(公告)日：2020-12-08

    申请号：US16534120

    申请日：2019-08-07

    Applicant: Micron Technology, Inc.

    Inventor： Mitsunari Sukekawa ,  Christopher J. Kawamura

    IPC: G11C11/4097 ,  G11C7/02 ,  H01L23/528 ,  G11C11/4091 ,  H01L27/108 ,  H01L25/18 ,  H01L23/58 ,  G11C7/18

    Abstract: Some embodiments include an integrated memory having a first bitline coupled with a first set of memory cells, and having a second bitline coupled with a second set of memory cells. The first and second bitlines are comparatively coupled through a sense amplifier. A first noise suppression line is adjacent to a region of the first bitline and extends parallel to the region of the first bitline. The first noise suppression line is electrically connected with one of the first and second bitlines and not with the other of the first and second bitlines. A second noise suppression line is adjacent to a region of the second bitline and extends parallel to the region of the second bitline. The second noise suppression line is electrically connected with the other of the first and second bitlines.

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