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公开(公告)号：US11610634B2
公开(公告)日：2023-03-21
申请号：US17324827
申请日：2021-05-19
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer
Abstract: The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine multiple data values. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two self-selecting multi-level memory cells (MLC) of the plurality of memory cells to determine multiple data values. The data values are determined by sensing a memory state of a first MLC using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing a memory state of a second MLC using a second sensing voltage in a sense window between the first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to the second memory state. The sequence of determining data values includes sensing the memory state of the first and the second MLCs using higher sensing voltages than the first and the second sensing voltages in subsequent sensing windows, in repeated iterations, until the state of the first and the second MLCs are determined. The first and second sensing voltages are selectably closer in the sense window to the first threshold voltage distribution or the second threshold voltage distribution.
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公开(公告)号：US20230081492A1
公开(公告)日：2023-03-16
申请号：US17950630
申请日：2022-09-22
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer
IPC: G11C13/00
Abstract: Methods, systems, and devices for parallel drift cancellation are described. In some instances, during a first duration, a first voltage may be applied to a word line to threshold one or more memory cells included in a first subset of memory cells. During a second duration, a second voltage may be applied to the word line to write a first logic state to one or more memory cells included in the first subset and to threshold one or more memory cells included in a second subset of memory cells. During a third duration, a third voltage may be applied to the word line to write a second logic state to one or more memory cells included in the second subset of memory cells.
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公开(公告)号：US20230027799A1
公开(公告)日：2023-01-26
申请号：US17881274
申请日：2022-08-04
Applicant: Micron Technology, Inc.
Inventor： Stephen W. Russell , Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer , Lorenzo Fratin
Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.
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公开(公告)号：US20220366974A1
公开(公告)日：2022-11-17
申请号：US17816612
申请日：2022-08-01
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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公开(公告)号：US11468930B2
公开(公告)日：2022-10-11
申请号：US17193227
申请日：2021-03-05
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Fabio Pellizzer
Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.
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Patent Agency Ranking
公开(公告)号：US20220319606A1
公开(公告)日：2022-10-06
申请号：US17221412
申请日：2021-04-02
Applicant: Micron Technology, Inc.
Inventor： Karthik Sarpatwari , Fabio Pellizzer , Nevil N. Gajera
Abstract: Systems, methods and apparatus to determine, in response to a command to write data into a set of memory cells, a programming mode of a set of memory cell to optimize performance in retrieving the data back from the set of memory cells. For example, based on usages of a memory region containing the memory cell set, a predictive model can be used to identify a combination of an amount of redundant information to be stored into the memory cells in the set and a programming mode of the memory cells to store the redundant information. Increasing the amount of redundant information can increase error recovery capability but increase bit error rate and/or increase time to read. The predictive model is trained to predict the combination to optimize read performance.
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公开(公告)号：US11374059B2
公开(公告)日：2022-06-28
申请号：US16892459
申请日：2020-06-04
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US20220122663A1
公开(公告)日：2022-04-21
申请号：US17511484
申请日：2021-10-26
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices for polarity-written cell architectures for a memory device are described. In an example, the described architectures may include memory cells that each include or are otherwise associated with a material configured to store one of a set of logic states based at least in part on a polarity of a write voltage applied to the material. Each of the memory cells may also include a cell selection component configured to selectively couple the material with an access line. In some examples, the material may include a chalcogenide, and the material may be configured to store each of the set of logic states in an amorphous state of the chalcogenide. In various examples, different logic states may be associated with different compositional distributions of the material of a respective memory cell, different threshold characteristics of the material of a respective memory cell, or other characteristics.
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公开(公告)号：US11302393B2
公开(公告)日：2022-04-12
申请号：US17024248
申请日：2020-09-17
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
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公开(公告)号：US11282895B2
公开(公告)日：2022-03-22
申请号：US16460875
申请日：2019-07-02
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Fabio Pellizzer , Lorenzo Fratin
IPC: H01L27/24 , H01L45/00 , H01L27/112
Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.
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