公开(公告)号：US20240385751A1

公开(公告)日：2024-11-21

申请号：US18787528

申请日：2024-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a program-erase cycle count associated with at least a portion of the plurality of memory cells. The processing device is further to erase, based on the value of the PEC count, less than a predetermined portion of free sets of memory cells to form an erased set of memory cells. The processing device is further to receive a programming command directed to at least a portion of the erased set of memory cells. The processing device is further to perform a programming operation with respect to the at least a portion of the erased set of memory cells.

公开(公告)号：US20240069735A1

公开(公告)日：2024-02-29

申请号：US17898333

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.

公开(公告)号：US11726671B2

公开(公告)日：2023-08-15

申请号：US17357436

申请日：2021-06-24

Applicant: Micron Technology, Inc.

Inventor： Guang Hu ,  Jianmin Huang ,  Zhengang Chen

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0679

Abstract: A method includes determining one or more quality attributes for memory cells of a memory device, receiving a memory access request involving data written to at least a portion of the memory cells, and determining whether the memory access request corresponds to a random read operation or a sequential read operation. The method further includes responsive to determining that the memory access request corresponds to a random read operation or responsive to determining that the one or more quality attributes for memory cells are greater than a threshold quality level, or both, selecting a read mode for use in performance of the random read operation and performing the random read operation using the selected read mode.

公开(公告)号：US20230040062A1

公开(公告)日：2023-02-09

申请号：US17966391

申请日：2022-10-14

Applicant: Micron Technology, Inc.

Inventor： Guang Hu

IPC: G06F3/06

Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.

公开(公告)号：US20220334754A1

公开(公告)日：2022-10-20

申请号：US17234227

申请日：2021-04-19

Applicant: Micron Technology, Inc.

Inventor： Guang Hu

IPC: G06F3/06

Abstract: A method includes determining respective memory access counts of a plurality of blocks of non-volatile memory cells that are grouped into a plurality of respective groups, comparing the respective memory access counts to respective memory access thresholds, determining a respective memory access count of a block of non-volatile memory cells exceeds a respective memory access threshold, and performing a media scan operation on the block of non-volatile memory cells.

公开(公告)号：US20220270702A1

公开(公告)日：2022-08-25

申请号：US17743989

申请日：2022-05-13

Applicant: Micron Technology, Inc.

Inventor： Guang Hu ,  Ting Luo ,  Chun Sum Yueng

IPC: G11C29/42 ,  G11C7/20 ,  G11C29/44

Abstract: A method includes determining whether a data reliability parameter associated with a set of memory cells is greater than a threshold data reliability parameter and in response to determining that the data reliability parameter is greater than the threshold data reliability parameter, performing an error recovery operation. The method further includes, subsequent to performing the error recovery operation, determining whether the data reliability parameter associated with the set of memory cells is less than the threshold data reliability parameter and in response to determining that the data reliability parameter is less than the threshold data reliability parameter, setting an offset associated with the error recovery operation as a default read voltage for the set of memory cells.

公开(公告)号：US20250104799A1

公开(公告)日：2025-03-27

申请号：US18788730

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Guang Hu ,  Xiangang Luo ,  Jianmin Huang

IPC: G11C29/00

Abstract: Aspects of the present disclosure configure a memory sub-system controller to generate virtual blocks using partial good blocks or portions of full blocks. The controller identifies a region of a set of memory components comprising a plurality of planes across a plurality of decks. The controller determines that a first memory block within a first deck associated with a first plane of the plurality of planes is a first partial good block (PGB), the first PGB including a portions categorized as being defective and portions categorized as being non-defective. The controller determines that a second memory block associated with a second plane is a full block (FB), the FB being categorized as non-defective. The controller generates a virtual block using the first PGB of the first memory block associated with the first plane and a portion of the FB of the second memory block associated with the second plane.

公开(公告)号：US20240404604A1

公开(公告)日：2024-12-05

申请号：US18733187

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： Jie Zhou ,  Xiangang Luo ,  Min Rui Ma ,  Guang Hu

IPC: G11C16/26 ,  G11C29/02 ,  G11C29/52

Abstract: Methods, systems, and devices for determining offsets for memory read operations are described. In response to a threshold quantity of pages failing initial reads but being successfully read using a same reference adjustment during re-reads, the offset responsible for the adjustment may be used as a first-applied offset for subsequent re-reads or a baseline offset for subsequent initial reads. After the initial reads begin using the reference adjustment, if a threshold quantity of pages fail initial reads, the offset used for the initial read may be adjusted to be the offset used to perform the successful re-reads. If an updated offset to use a baseline is not identified, the baseline offset may be cleared so the original reference may again be used without adjustment for initial reads.

公开(公告)号：US20240370181A1

公开(公告)日：2024-11-07

申请号：US18651781

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： Yuqi Zhu ,  Guang Hu ,  Ting Luo ,  Xiangang Luo

IPC: G06F3/06

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to dynamically allocate blocks from a free block pool. The controller generates a free block pool that includes a collection of full blocks and a collection of partial good blocks (PGBs) of a set of memory components, a size of a full block in the collection of full blocks corresponding to a combination of two or more PGBs of the collection of PGBs. The controller receives a request to write data. The controller allocates an individual full block from the collection of full blocks or an individual PGB from the collection of PGBs based on determining whether the request to write the data has been received from the host device or the controller of the memory sub-system.

公开(公告)号：US20240242760A1

公开(公告)日：2024-07-18

申请号：US18421729

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Tao Jiang ,  Bo Zhou ,  Guang Hu

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/4099 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4096

Abstract: Methods, systems, and devices for reference voltage adjustment for word line groups are described. In some examples, one or more components of a memory system may determine a duration that data has been stored to one or more memory cells. Based on the duration, a voltage value of one or more reference voltages may be adjusted accordingly. For example, a voltage value of one or more reference voltages may be adjusted based on the duration. Moreover, the reference voltage values may be adjusted differently in response to the memory cells having stored data for a relatively longer duration, as opposed to memory cells that have stored data for a relatively shorter duration. The adjusted reference voltages may be used during a subsequent read operation. The voltage value of the one or more reference voltages may be adjusted on a word-line group by word-line group basis.