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公开(公告)号：US12210448B2
公开(公告)日：2025-01-28
申请号：US18037631
申请日：2022-09-01
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Jianmin Huang , Xiaolai Zhu , Deping He , Kulachet Tanpairoj , Hong Lu , Chun Sum Yeung
IPC: G06F12/02
Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.
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公开(公告)号：US20240273023A1
公开(公告)日：2024-08-15
申请号：US18630779
申请日：2024-04-09
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Deping He , Min Rui Ma
IPC: G06F12/0804 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/30
CPC classification number: G06F12/0804 , G11C16/10 , G11C16/26 , G11C16/30 , G06F2212/1032 , G11C16/0483
Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.
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公开(公告)号：US11983112B2
公开(公告)日：2024-05-14
申请号：US17646253
申请日：2021-12-28
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Deping He , Min Rui Ma
CPC classification number: G06F12/0804 , G11C16/10 , G11C16/26 , G11C16/30 , G06F2212/1032 , G11C16/0483
Abstract: Methods, systems, and devices for techniques for enhanced system performance after retention loss are described. A memory system may program a page of memory cells in response to receiving a power down notification. As part of the programming, the memory system may record an indication of a voltage threshold of the page and power down for a duration of time, during which the memory system may experience retention loss. Upon powering on, the memory device may compare the voltage threshold of the page to the indication stored prior to powering down and determine a voltage offset for one or more blocks of the memory system. In some cases, the memory system may use the voltage offset to determine a starting bin, and may initiate a bin scan to determine a final bin for the one or more blocks.
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公开(公告)号：US20240036753A1
公开(公告)日：2024-02-01
申请号：US17877240
申请日：2022-07-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wai Leong Chin , Francis Chee Khai Chew , Trismardawi Tanadi , Chun Sum Yeung , Lawrence Dumalag , Ekamdeep Singh
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0653 , G06F3/0604 , G06F3/0679
Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.
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公开(公告)号：US11656940B2
公开(公告)日：2023-05-23
申请号：US17574059
申请日：2022-01-12
Applicant: Micron Technology, Inc.
Inventor： Deping He , Chun Sum Yeung , Jonathan S. Parry
CPC classification number: G06F11/1068 , G06F3/064 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/076 , G06F11/0772
Abstract: Methods, systems, and devices for techniques for managing temporarily retired blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. For example, a controller may determine an existence of the error and may temporarily retire the block. A media management operation may be performed on the temporarily retired block and, depending on one or more characteristics of the error, the temporarily retired block may be enabled or retired.
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Patent Agency Ranking
公开(公告)号：US11599300B2
公开(公告)日：2023-03-07
申请号：US17234095
申请日：2021-04-19
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Guang Hu , Ting Luo , Tao Liu
IPC: G06F3/06
Abstract: A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.
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公开(公告)号：US11373729B2
公开(公告)日：2022-06-28
申请号：US16903066
申请日：2020-06-16
Applicant: Micron Technology, Inc.
Inventor： Tao Liu , Chun Sum Yeung , Xiangang Luo
Abstract: A replacement block pool for a memory device is established. The replacement block pool comprises one or more valid blocks from a set of valid blocks in the memory device determined based on a constraint defining a minimum number of valid blocks for the memory device. A grown bad block is detected in the memory device. The grown bad block is replaced with a replacement block from the replacement block pool in response to detecting the grown bad block.
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公开(公告)号：US20250086055A1
公开(公告)日：2025-03-13
申请号：US18890418
申请日：2024-09-19
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Jonathan S. Parry , Deping He , Xiangang Luo , Reshmi Basu
IPC: G06F11/10
Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.
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公开(公告)号：US12079481B2
公开(公告)日：2024-09-03
申请号：US17898333
申请日：2022-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Chun Sum Yeung , Deping He , Ting Luo , Guang Hu , Jonathan S. Parry
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0653 , G06F3/0679
Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.
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公开(公告)号：US11501840B1
公开(公告)日：2022-11-15
申请号：US17243386
申请日：2021-04-28
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Devin M. Batutis
Abstract: A method is described that includes determining, by a memory subsystem controller of a memory device, a number of memory cells from a set of memory cells that are in a programmed state. The memory subsystem controller further compares the number of memory cells from the set of memory cells that are in the programmed state to a proximity disturb threshold and in response to determining that the number satisfies the proximity disturb threshold, performs a remediation operation on user data stored in the set of memory cells.
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