公开(公告)号：US20240385751A1

公开(公告)日：2024-11-21

申请号：US18787528

申请日：2024-07-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a program-erase cycle count associated with at least a portion of the plurality of memory cells. The processing device is further to erase, based on the value of the PEC count, less than a predetermined portion of free sets of memory cells to form an erased set of memory cells. The processing device is further to receive a programming command directed to at least a portion of the erased set of memory cells. The processing device is further to perform a programming operation with respect to the at least a portion of the erased set of memory cells.

公开(公告)号：US20240363185A1

公开(公告)日：2024-10-31

申请号：US18656177

申请日：2024-05-06

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

IPC: G11C29/42 ,  G06F11/07 ,  G11C29/12 ,  G11C29/20 ,  G11C29/44

CPC classification number: G11C29/42 ,  G06F11/076 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/4401

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

公开(公告)号：US20240345727A1

公开(公告)日：2024-10-17

申请号：US18610028

申请日：2024-03-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Wenjun Wu

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices for data compression for mapping tables are described. A memory system may store a table that includes mappings between a set of logical block addresses and a set of physical block addresses. The table may be stored to volatile memory of the memory system and each entry may include a subset of physical block addresses and one or more logical block addresses that correspond to the subset of physical block addresses. In some implementations, a quantity of the entries that each include the subset of physical block addresses and the one or more logical block addresses may be determined based on dividing the set of physical block addresses by a factor. Similarly, a size of the entries may be determined based on dividing the set of physical block addresses by the factor.

公开(公告)号：US20240311053A1

公开(公告)日：2024-09-19

申请号：US18595590

申请日：2024-03-05

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0679

Abstract: Methods, systems, and devices for managing power consumption associated with communicating data in a memory system are described. A memory system may selectively reduce a periodicity of a clock signal for one or more types of write operations, which may improve power consumption associated with data transfer rates during the one or more types of write operations. For example, the memory system may modify the clock signal for triple-level cell (TLC) write operations. The memory system reduce a periodicity of the clock signal to improve performance for TLC write operations by trading communication speed for internal array performance. Additionally, or alternatively, some media management operations performed by the memory system that involve transferring data to higher-density memory cells may trigger the memory system to modify the clock signal.

公开(公告)号：US11966600B2

公开(公告)日：2024-04-23

申请号：US17725119

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0614 ,  G06F3/0641 ,  G06F3/0653 ,  G06F3/0683

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.

公开(公告)号：US11960398B2

公开(公告)日：2024-04-16

申请号：US16999985

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/00 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0882 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F11/1068 ,  G06F11/3037 ,  G06F12/0882 ,  G06F12/0891

Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.

公开(公告)号：US11942174B2

公开(公告)日：2024-03-26

申请号：US17574024

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Chun S. Yeung ,  Deping He ,  Jonathan S. Parry

IPC: G11C29/42 ,  G11C7/04 ,  G11C29/12 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C7/04 ,  G11C29/1201 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

公开(公告)号：US20240069735A1

公开(公告)日：2024-02-29

申请号：US17898333

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.

公开(公告)号：US11886266B2

公开(公告)日：2024-01-30

申请号：US17736886

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Yanming Liu ,  Deping He ,  Hua Tan

IPC: G06F1/00 ,  G06F1/3225 ,  G06F1/3296 ,  G06F3/06 ,  G06F1/3203

CPC classification number: G06F1/3225 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0659 ,  G06F1/3203 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.

公开(公告)号：US20230418491A1

公开(公告)日：2023-12-28

申请号：US17846761

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Bo Zhou ,  Caixia Yang

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/061 ,  G06F3/0679

Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.