公开(公告)号：US20230143181A1

公开(公告)日：2023-05-11

申请号：US16968371

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Hui Yang ,  Mauro Luigi Sali

IPC: G06F3/06 ,  G06F12/0815 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0815 ,  G06F12/0253 ,  G06F2212/1016

Abstract: Upon receipt of a synchronize cache command, valid host data size in the SRAM write buffer is checked. If the valid data size is greater than a predetermined value, valid host data in the SRAM write buffer is flushed directly into an open MLC block based on a one-pass transfer program. However, if the valid host data size is less than the predetermined value, the host data is not flushed to an open MLC block but is instead flushed into a temporary storage location to satisfy the command specifications for a command to synchronize a cache. The host data is maintained in the SRAM write buffer, which receives additional data until full. Once full, the host data in the SRAM write buffer is transferred to an open MLC block in one-pass. If the host data in the write buffer is lost, it may be recovered from the temporary storage location.

公开(公告)号：US20220397953A1

公开(公告)日：2022-12-15

申请号：US17736886

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Junjun Wang ,  Yanming Liu ,  Deping He ,  Hua Tan

IPC: G06F1/3225 ,  G06F1/3296 ,  G06F3/06

Abstract: Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.

公开(公告)号：US20240319884A1

公开(公告)日：2024-09-26

申请号：US18620773

申请日：2024-03-28

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Lingye Zhou

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0673

Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.

公开(公告)号：US11972109B2

公开(公告)日：2024-04-30

申请号：US17283495

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Lingye Zhou

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0673

Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. To avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. The memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. If the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.

公开(公告)号：US20240054070A1

公开(公告)日：2024-02-15

申请号：US18268292

申请日：2020-12-23

Applicant: Micron Technology, Inc

Inventor： Hua Tan ,  Zhen Shu ,  Nicola Colella

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A memory device comprises a memory array and a memory controller operatively coupled to the memory array. The memory controller includes a processor configured to initiate read operations to the memory array; compare the number of rad operations to a predetermined threshold number of read operations; initiate scanning memory pages of a block of memory cells for errors in response to reaching the threshold number of read operations for the block; and iteratively change the threshold number to a new threshold number, perform the new threshold number of read operations on the block of memory cells, and error scan memory pages associated with the last read operation of the new threshold number of rad operations.

公开(公告)号：US11763899B2

公开(公告)日：2023-09-19

申请号：US17132490

申请日：2020-12-23

Applicant: Micron Technology, Inc.

Inventor： Jun Jun Wang ,  Hua Tan

IPC: G11C16/34 ,  G11C29/44 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3431 ,  G11C16/08 ,  G11C16/26 ,  G11C29/44

Abstract: Methods, systems, devices, and computer-readable media for performing read disturb management of a memory device. A method includes retrieving a value of a read counter for a block associated with a read request issued to a memory array; refreshing valid word lines in the block if the value of the read counter exceeds a first threshold; identifying a set of valid word lines in the block if the value of the read counter exceeds a second threshold, the second threshold lower than the first threshold; identifying a subset of the set of valid word lines, the subset of the set of valid word lines including word lines having an error rate above a pre-configured error rate threshold; and refreshing the subset of the set of valid word lines.

公开(公告)号：US20230046402A1

公开(公告)日：2023-02-16

申请号：US17580333

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Fangwen Zhou ,  Wenjing Chen

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for memory operations are described. A first set of commands may be received for accessing a memory device. The first set of commands may include non-consecutive logical addresses that correspond to consecutively indexed physical addresses. A determination that the non-consecutive logical addresses correspond to consecutively indexed physical addresses may be determined based on a first mapping stored in a volatile memory. A second mapping may be transferred to the volatile memory based on the determination. The second mapping may include an indication of whether information stored at a set of physical address is valid. A second set of commands including non-consecutive logical addresses may be received for accessing the memory device. Data for the second set of commands that include the non-consecutive logical addresses may be retrieved from the memory device using the second mapping.

公开(公告)号：US11379367B2

公开(公告)日：2022-07-05

申请号：US16952813

申请日：2020-11-19

Applicant: Micron Technology, Inc.

Inventor： Nicola Colella ,  Antonino Pollio ,  Hua Tan

IPC: G06F12/00 ,  G06F12/0802 ,  G06F12/02

Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

公开(公告)号：US20210391013A1

公开(公告)日：2021-12-16

申请号：US17458211

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Hua Tan ,  Jingxun Eric Wu ,  Yingying Zhu ,  Hui Yang ,  Bo Zhou

IPC: G11C16/10 ,  G11C16/04 ,  G06F3/06 ,  G11C16/26 ,  G11C16/06 ,  G11C29/10 ,  G11C29/50

Abstract: A memory device comprises a memory array including memory cells, a temperature sensing circuit, and a memory control unit operatively coupled to the memory array. The memory control unit includes a processor. The processor is configured to receive temperature information from the temperature sensing circuit, initiate programming of the memory cells with data using a first threshold voltage distribution when the temperature information indicates an operating temperature is in a first temperature range, and initiate programming of the memory cells with data using a second threshold voltage distribution when the temperature information indicates the operating temperature is in a second temperature range.