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    Initialization techniques for memory devices
    1.
    发明授权
    Initialization techniques for memory devices 有权

    公开(公告)号：US11238940B1

    公开(公告)日：2022-02-01

    申请号：US16952880

    申请日：2020-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Antonino Pollio ,  Giuseppe Vito Portacci ,  Mauro Luigi Sali ,  Alessandro Magnavacca

    IPC: G11C16/20 ,  G11C16/16 ,  G11C29/42 ,  G11C29/14 ,  G11C16/26

    Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.

    WRITE BUFFER CONTROL IN MANAGED MEMORY SYSTEM
    4.
    发明公开
    WRITE BUFFER CONTROL IN MANAGED MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230143181A1

    公开(公告)日：2023-05-11

    申请号：US16968371

    申请日：2019-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Hua Tan ,  Hui Yang ,  Mauro Luigi Sali

    IPC: G06F3/06 ,  G06F12/0815 ,  G06F12/02

    CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0815 ,  G06F12/0253 ,  G06F2212/1016

    Abstract: Upon receipt of a synchronize cache command, valid host data size in the SRAM write buffer is checked. If the valid data size is greater than a predetermined value, valid host data in the SRAM write buffer is flushed directly into an open MLC block based on a one-pass transfer program. However, if the valid host data size is less than the predetermined value, the host data is not flushed to an open MLC block but is instead flushed into a temporary storage location to satisfy the command specifications for a command to synchronize a cache. The host data is maintained in the SRAM write buffer, which receives additional data until full. Once full, the host data in the SRAM write buffer is transferred to an open MLC block in one-pass. If the host data in the write buffer is lost, it may be recovered from the temporary storage location.

    INITIALIZATION TECHNIQUES FOR MEMORY DEVICES
    5.
    发明申请
    INITIALIZATION TECHNIQUES FOR MEMORY DEVICES 有权

    公开(公告)号：US20220223211A1

    公开(公告)日：2022-07-14

    申请号：US17586526

    申请日：2022-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Antonino Pollio ,  Giuseppe Vito Portacci ,  Mauro Luigi Sali ,  Alessandro Magnavacca

    IPC: G11C16/20 ,  G11C16/16 ,  G11C29/42 ,  G11C29/14 ,  G11C16/26

    Abstract: Methods, systems, and devices for initialization techniques for memory devices are described. A memory system may include a memory array on a first die and a controller on a second die, where the second die is coupled with the first die. The controller may perform an initialization procedure based on operating instructions stored within the memory system. For example, the controller may read a first set of operating instructions from read-only memory on the second die. The controller may obtain a second set of operating instructions stored at a memory block of the memory array on the first die, with the memory block indicated by the first set of operating instructions. The controller may complete or at least further the initialization procedure based on the second set of operating instructions.

    MEMORY SYSTEM TESTER USING TEST PAD REAL TIME MONITORING
    6.
    发明申请
    MEMORY SYSTEM TESTER USING TEST PAD REAL TIME MONITORING 有权

    公开(公告)号：US20220101938A1

    公开(公告)日：2022-03-31

    申请号：US17549377

    申请日：2021-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Vigilante ,  Gianluca Scalisi ,  Andrea Pozzato ,  Andrea Salvioni ,  Mauro Luigi Sali

    IPC: G11C29/38 ,  G11C29/36 ,  G11C16/04

    Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

    Adjustable NAND write performance
    8.
    发明授权
    Adjustable NAND write performance 有权

    公开(公告)号：US11526277B2

    公开(公告)日：2022-12-13

    申请号：US17157410

    申请日：2021-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Mauro Luigi Sali ,  Stefano Falduti ,  Ugo Russo

    IPC: G06F3/06

    Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

    ADJUSTABLE NAND WRITE PERFORMANCE
    9.
    发明申请
    ADJUSTABLE NAND WRITE PERFORMANCE 有权

    公开(公告)号：US20210141530A1

    公开(公告)日：2021-05-13

    申请号：US17157410

    申请日：2021-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Mauro Luigi Sali ,  Stefano Falduti ,  Ugo Russo

    IPC: G06F3/06

    Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

    Adjustable NAND write performance
    10.
    发明授权
    Adjustable NAND write performance 有权

    公开(公告)号：US10901622B2

    公开(公告)日：2021-01-26

    申请号：US16236040

    申请日：2018-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Mauro Luigi Sali ,  Stefano Falduti ,  Ugo Russo

    IPC: G06F3/06

    Abstract: Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.

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