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公开(公告)号：US20230084668A1
公开(公告)日：2023-03-16
申请号：US17447490
申请日：2021-09-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tae H. Kim , Christopher J. Kawamura , Jiyun Li
IPC: G11C11/4091
Abstract: Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.
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公开(公告)号：US20210358539A1
公开(公告)日：2021-11-18
申请号：US17387934
申请日：2021-07-28
Applicant: Micron Technology, Inc.
Inventor： Timothy B. Cowles , Dean D. Gans , Jiyun Li , Nathaniel J. Meier , Randall J. Rooney
IPC: G11C11/406
Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
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公开(公告)号：US20210183411A1
公开(公告)日：2021-06-17
申请号：US16710687
申请日：2019-12-11
Applicant: Micron Technology, Inc.
Inventor： Jiyun Li
Abstract: An example apparatus includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source/drain region, a second source/drain region, and a gate opposing a channel connecting the first source/drain region and the second source/drain region. Each access device further includes a storage node. The example apparatus further includes a plurality of sense lines coupled to the first source/drain region of a different respective memory cell of the array of memory cells. The example apparatus further includes a plurality of access lines, wherein each access line includes at least one conductive pathway formed between the access line and a source/drain region of an access device coupled to the access line. The example apparatus further includes a shunt sense line coupled to the additional access device where the conductive pathway is formed.
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公开(公告)号：US12159682B2
公开(公告)日：2024-12-03
申请号：US17805090
申请日：2022-06-02
Applicant: Micron Technology, Inc.
Abstract: Multi-level cells, and related methods, arrays, devices, and systems, are described. A device may include a memory array including a first reference section including a first number of memory cells and a first reference digit line. The memory array may also include a second reference section including a second number of memory cells and a second reference digit line. The memory array may also include a target section including a memory cell. The target section may further include a first digit line coupled to the memory cell via a first switch, wherein the first digit line is further coupled to the first reference digit line via a first sense amplifier. The target section may also include a second digit line coupled to the first digit line via a second switch, wherein the second digit line is further coupled to the second reference digit line via a second sense amplifier.
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公开(公告)号：US20240282370A1
公开(公告)日：2024-08-22
申请号：US18393334
申请日：2023-12-21
Applicant: Micron Technology, Inc.
IPC: G11C11/56 , G11C11/4091 , G11C11/4094
CPC classification number: G11C11/5628 , G11C11/4091 , G11C11/4094
Abstract: Memory devices including tri-state memory cells are disclosed. A memory device may include a first tri-state cell that may store a first voltage level that is one of three voltage levels, a second tri-state cell that may store a second voltage level that is one of the three voltage levels, and three input/output lines that may access the memory device. The three input/output lines may carry three respective binary signals based on the first voltage level and the second voltage level. A memory device may include a bank including a number of continuous arrays of tri-state memory cells. Each of the tri-state memory cells may be accessible by a respective bit line. Groups of the bit lines may be associated with respective column-select lines. The bank may include a number of sub-word-line drivers interspersed between the number of continuous arrays. Associated systems and methods are also disclosed.
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Patent Agency Ranking
公开(公告)号：US20220164251A1
公开(公告)日：2022-05-26
申请号：US17100775
申请日：2020-11-20
Applicant: Micron Technology, Inc.
Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.
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公开(公告)号：US11200942B2
公开(公告)日：2021-12-14
申请号：US16549942
申请日：2019-08-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Matthew D. Jenkinson , Jiyun Li , Dennis G. Montierth , Nathaniel J. Meier
IPC: G11C11/408 , G11C8/16 , H03K3/03 , G06F12/0802
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for lossy row access counting. Row addresses along a to address bus may be sampled. When the row address is sampled it may be compared to a plurality of stored addresses in a data storage unit. If the sampled address matches one of the stored addresses, a count value associated with that address may be updated in a first direction (such as being increased). Periodically, all of the count values may also be updated in a second direction (for example, decreased).
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公开(公告)号：US11127436B2
公开(公告)日：2021-09-21
申请号：US16710687
申请日：2019-12-11
Applicant: Micron Technology, Inc.
Inventor： Jiyun Li
Abstract: An example apparatus includes an array of memory cells. Each memory cell includes an access device. Each access device includes a first source/drain region, a second source/drain region, and a gate opposing a channel connecting the first source/drain region and the second source/drain region. Each access device further includes a storage node. The example apparatus further includes a plurality of sense lines coupled to the first source/drain region of a different respective memory cell of the array of memory cells. The example apparatus further includes a plurality of access lines, wherein each access line includes at least one conductive pathway formed between the access line and a source/drain region of an access device coupled to the access line. The example apparatus further includes a shunt sense line coupled to the additional access device where the conductive pathway is formed.
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19.发明申请公开(公告)号：US20210249416A1
公开(公告)日：2021-08-12
申请号：US16785942
申请日：2020-02-10
Applicant: Micron Technology, Inc.
Inventor： Jiyun Li , Scott J. Derner
IPC: H01L27/108 , H01L23/522 , G11C11/4074 , G11C11/4091 , G11C11/408
Abstract: Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.
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公开(公告)号：US11069385B1
公开(公告)日：2021-07-20
申请号：US16835797
申请日：2020-03-31
Applicant: Micron Technology, inc.
Inventor： Jiyun Li , Scott J. Derner
IPC: G11C11/24 , G11C7/08 , G11C11/4091 , H01L27/108
Abstract: Some embodiments include an integrated assembly having a second deck over a first deck. A first true digit line has first and second segments along the first deck. A first complementary digit line has third and fourth segments along the second deck. The first true digit line is comparatively compared to the first complementary digit line. A second true digit line has a third region along the first deck and a fourth region along the second deck. The third region is adjacent the first segment, and the fourth region is adjacent the third segment. A second complementary digit line has a fifth region along the first deck and has a sixth region along the second deck. The fifth region is adjacent the second segment, and the sixth region is adjacent the fourth segment. The second true digit line is comparatively compared to the second complementary digit line.
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