公开(公告)号：US20180255001A1

公开(公告)日：2018-09-06

申请号：US15447867

申请日：2017-03-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEREMY CHRITZ ,  TAMARA SCHMITZ ,  JOHN L. WATSON ,  JOHN SCHROETER ,  FA-LONG LUO ,  JAIME CUMMINS

IPC: H04L12/933 ,  H04W4/00 ,  H04B7/04

CPC classification number: H04L49/109 ,  H04B7/04 ,  H04W4/80 ,  H04W84/042

Abstract: An apparatus is disclosed. The apparatus comprises a plurality of antennas and an integrated circuit chip coupled to the plurality of antennas, and is configured to process cellular signals received from the plurality of antennas in accordance with a cellular communication protocol and to process radio frequency identification (RFID) signals received from the plurality of antennas in accordance with an RFD protocol.

公开(公告)号：US20230262731A1

公开(公告)日：2023-08-17

申请号：US18306694

申请日：2023-04-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FA-LONG LUO ,  JAIME CUMMINS ,  TAMARA SCHMITZ ,  JEREMY CHRITZ

IPC: H04W72/29 ,  H04W88/08

CPC classification number: H04W72/29 ,  H04W88/085 ,  Y02D30/70

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of configuration modes for baseband units (BBU) and remote radio heads (RRH). For example, a computing system including a BBU and a RRH may receive a configuration mode selection including information indicative of a configuration mode for respective processing units of the BBU and the RRH. The computing system allocates the respective processing units to perform wireless processing stages associated with a wireless protocol. The BBU and/or the RRH may generate an output data stream based on the mixing of coefficient data with input data at the BBU and/or the RRH. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

公开(公告)号：US20230208449A1

公开(公告)日：2023-06-29

申请号：US18179317

申请日：2023-03-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FA-LONG LUO ,  JAIME CUMMINS ,  TAMARA SCHMITZ

IPC: H03M13/00 ,  H03M13/15 ,  G06N3/08 ,  G06F17/18 ,  H03M13/11 ,  G06F18/23213 ,  G06N3/047

CPC classification number: H03M13/6597 ,  H03M13/1515 ,  H03M13/152 ,  G06N3/08 ,  G06F17/18 ,  H03M13/1102 ,  G06F18/23213 ,  G06N3/047

Abstract: Examples described herein utilize multi-layer neural networks to decode encoded data (e.g., data encoded using one or more encoding techniques). The neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous in many systems employing the neural network decoders. In this manner, neural networks described herein may be used to implement error code correction (ECC) decoders.

公开(公告)号：US20230205453A1

公开(公告)日：2023-06-29

申请号：US18170753

申请日：2023-02-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DAVID HULTON ,  JEREMY CHRITZ ,  TAMARA SCHMITZ

IPC: G06F3/06 ,  G06F13/16 ,  H04L9/06 ,  G06N3/08 ,  G06F18/214 ,  G06F18/2413

CPC classification number: G06F3/0658 ,  G06F3/0679 ,  G06F3/0607 ,  G06F13/1668 ,  H04L9/0643 ,  G06N3/08 ,  G06F18/2155 ,  G06F18/24147 ,  G06F2213/0026

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

公开(公告)号：US20220171634A1

公开(公告)日：2022-06-02

申请号：US17673712

申请日：2022-02-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEREMY CHRITZ ,  TAMARA SCHMITZ ,  FA-LONG LUO ,  DAVID HULTON

IPC: G06F9/448 ,  G06F9/38 ,  G06F12/0842 ,  G06F15/82 ,  G06F9/50

Abstract: Methods, apparatuses, and systems for implementing data flows in a processor are described herein. A data flow manager may be configured to generate a configuration packet for a compute operation based on status information regarding multiple processing elements of the processor. Accordingly, multiple processing elements of a processor may concurrently process data flows based on the configuration packet. For example, the multiple processing elements may implement a mapping of processing elements to memory, while also implementing identified paths, through the processor, for the data flows. After executing the compute operation at certain processing elements of the processor, the processing results may be provided. In speech signal processing operations, the processing results may be compared to phonemes to identify such components of human speech in the processing results. Once dynamically identified, the processing elements may continue comparing additional components of human speech to facilitate processing of an audio recording, for example.

公开(公告)号：US20210182074A1

公开(公告)日：2021-06-17

申请号：US17184945

申请日：2021-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FA-LONG LUO ,  TAMARA SCHMITZ ,  JEREMY CHRITZ ,  JAIME CUMMINS

IPC: G06F9/38 ,  G06F15/78

Abstract: Examples described herein include systems and methods which include an apparatus comprising a plurality of configurable logic units and a plurality of switches, with each switch being coupled to at least one configurable logic unit of the plurality of configurable logic units. The apparatus further includes an instruction register configured to provide respective switch instructions of a plurality of switch instructions to each switch based on a computation to be implemented among the plurality of configurable logic units. For example, the switch instructions may include allocating the plurality of configurable logic units to perform the computation and activating an input of the switch and an output of the switch to couple at least a first configurable logic unit and a second configurable logic unit. In various embodiments, configurable logic units can include arithmetic logic units (ALUs), bit manipulation units (BMUs), and multiplier-accumulator units (MACs).

公开(公告)号：US20200235794A1

公开(公告)日：2020-07-23

申请号：US16844178

申请日：2020-04-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FA-LONG LUO ,  TAMARA SCHMITZ ,  JEREMY CHRITZ ,  JAIME CUMMINS

IPC: H04B7/0456 ,  H04B7/08 ,  G06F17/15 ,  H04B7/0413

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of an autocorrelation calculator. An electronic device including an autocorrelation calculator may be configured to calculate an autocorrelation matrix including an autocorrelation of symbols indicative of a first radio frequency (“RF”) signal and a second RF signal. The electronic device may calculate the autocorrelation matrix based on a stored autocorrelation matrix and the autocorrelation of symbols indicative of the first RF signal and symbols indicative of the second RF signal. The stored autocorrelation matrix may represent another received signal at a different time period than a time period of the first and second RF signals. Examples of the systems and methods may facilitate the processing of data for wireless and may utilize less memory space than a device than a scheme that stores and calculates autocorrelation from a large dataset computed from various time points.

公开(公告)号：US20180307483A1

公开(公告)日：2018-10-25

申请号：US15493551

申请日：2017-04-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FA-LONG LUO ,  TAMARA SCHMITZ ,  JEREMY CHRITZ ,  JAIME CUMMINS

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30098 ,  G06F9/30145

Abstract: Examples described herein include systems and methods which include an apparatus comprising a plurality of configurable logic units and a plurality of switches, with each switch being coupled to at least one configurable logic unit of the plurality of configurable logic units. The apparatus further includes an instruction register configured to provide respective switch instructions of a plurality of switch instructions to each switch based on a computation to be implemented among the plurality of configurable logic units. For example, the switch instructions may include allocating the plurality of configurable logic units to perform the computation and activating an input of the switch and an output of the switch to couple at least a first configurable logic unit and a second configurable logic unit. In various embodiments, configurable logic units can include arithmetic logic units (ALUs), bit manipulation units (BMUs), and multiplier-accumulator units (MACs).

公开(公告)号：US20220068430A1

公开(公告)日：2022-03-03

申请号：US17454443

申请日：2021-11-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DAVID HULTON ,  TAMARA SCHMITZ ,  JONATHAN D. HARMS ,  JEREMY CHRITZ ,  KEVIN MAJERUS

IPC: G11C29/00 ,  G06F12/126 ,  G06F12/02 ,  G06F3/06

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

公开(公告)号：US20220060226A1

公开(公告)日：2022-02-24

申请号：US17453914

申请日：2021-11-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FA-LONG LUO ,  TAMARA SCHMITZ ,  JEREMY CHRITZ ,  JAIME CUMMINS

IPC: H04B7/0456 ,  H04B7/08 ,  G06F17/15 ,  H04B7/0413

Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of an autocorrelation calculator. An electronic device including an autocorrelation calculator may be configured to calculate an autocorrelation matrix including an autocorrelation of symbols indicative of a first narrowband Internet of Things (IoT) transmission and a second narrowband IoT transmission. The electronic device may calculate the autocorrelation matrix based on a stored autocorrelation matrix and the autocorrelation of symbols indicative of the first narrowband IoT transmission and symbols indicative of the second narrowband IoT transmission. The stored autocorrelation matrix may represent another received signal at a different time period than a time period of the first and second narrowband IoT transmission. Examples of the systems and methods may facilitate the processing of data for wireless and may utilize less memory space than a device than a scheme that stores and calculates autocorrelation from a large dataset computed from various time points.