公开(公告)号：US20240202114A1

公开(公告)日：2024-06-20

申请号：US18591777

申请日：2024-02-29

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Tang ,  David Ebsen ,  Ying Huang ,  Sundararajan Sankaranarayanan

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0253 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.

公开(公告)号：US12189958B2

公开(公告)日：2025-01-07

申请号：US17898160

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

IPC: G06F3/06

Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

公开(公告)号：US12124739B2

公开(公告)日：2024-10-22

申请号：US17949333

申请日：2022-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler L. Betz ,  Sundararajan N. Sankaranarayanan ,  Roberto Izzi ,  Massimo Zucchinali ,  Xiangyu Tang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

公开(公告)号：US20240256136A1

公开(公告)日：2024-08-01

申请号：US18408836

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： Haibo Li ,  Xiangyu Tang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.

公开(公告)号：US20240069809A1

公开(公告)日：2024-02-29

申请号：US17949333

申请日：2022-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler L. Betz ,  Sundararajan N. Sankaranarayanan ,  Roberto Izzi ,  Massimo Zucchinali ,  Xiangyu Tang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.