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    ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS
    1.
    发明公开
    ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS 审中-公开

    公开(公告)号：US20240069738A1

    公开(公告)日：2024-02-29

    申请号：US17898160

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0679

    Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

    MEMORY WITH SWITCHABLE CHANNELS
    2.
    发明公开
    MEMORY WITH SWITCHABLE CHANNELS 审中-公开

    公开(公告)号：US20240069721A1

    公开(公告)日：2024-02-29

    申请号：US17823909

    申请日：2022-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Sundararajan Sankaranarayanan ,  Chulbum Kim ,  Xiangyu Tang

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Memory with switchable channels is disclosed herein. In one embodiment, a system comprises a controller, a plurality of memory dies, and a switch matrix. The switch matrix is coupled to the controller via two or more controller-side channels, and to the plurality of memory dies via a set of memory-side channels. The switch matrix is configured to selectively couple each controller-side channel of the two or more controller-side channels to each memory-side channel of the set of memory-side channels to provide dynamically configurable connections between the controller and one or more memory dies of the plurality of memory dies.

    MEMORY DEVICES INCLUDING IDLE TIME PREDICTION
    6.
    发明申请
    MEMORY DEVICES INCLUDING IDLE TIME PREDICTION 有权

    公开(公告)号：US20250028487A1

    公开(公告)日：2025-01-23

    申请号：US18906236

    申请日：2024-10-04

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tyler L. Betz ,  Sundararajan N. Sankaranarayanan ,  Roberto Izzi ,  Massimo Zucchinali ,  Xiangyu Tang

    IPC: G06F3/06

    Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

    Data burst queue management
    8.
    发明授权
    Data burst queue management 有权

    公开(公告)号：US12248411B2

    公开(公告)日：2025-03-11

    申请号：US18144957

    申请日：2023-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Xiangyu Tang ,  Daniel Jerre Hubbard

    IPC: G06F13/16 ,  G06F12/0879 ,  G06F13/32

    Abstract: Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.

    MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE
    9.
    发明申请
    MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE 有权

    公开(公告)号：US20250077416A1

    公开(公告)日：2025-03-06

    申请号：US18781838

    申请日：2024-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Huai-Yuan Tseng ,  Xiangyu Tang ,  Eric N. Lee ,  Haibo Li ,  Kishore Kumar Muchherla ,  Akira Goda

    IPC: G06F12/02

    Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

    ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS
    10.
    发明申请
    ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS 有权

    公开(公告)号：US20250077086A1

    公开(公告)日：2025-03-06

    申请号：US18950798

    申请日：2024-11-18

    Applicant: Micron Technology, Inc.

    Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

    IPC: G06F3/06

    Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, wherein the memory sub-system controller provides a plurality of channel mappings, wherein a first channel mapping of the plurality of channel mappings identifies a first controller channel of the plurality of controller channels and one or more first memory channels of a plurality of memory channels, and wherein a second channel mapping of the plurality of channel mappings identifies a second controller channel of the plurality of controller channels and one or more second memory channels of the plurality of memory channels; one or more memory devices comprising the plurality of memory channels, wherein the one or more memory devices comprise a plurality of memory dies, wherein each memory channel of the plurality of memory channels corresponds to a respective one of the plurality of memory dies; and a channel switch circuit coupled between the plurality of the controller channels and the plurality of memory channels, wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing.

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