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公开(公告)号：US20220382487A1
公开(公告)日：2022-12-01
申请号：US17771668
申请日：2019-12-31
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer , Xinghui Duan , Massimo Zucchinali
Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918). The operations additionally cause the prediction system (190) to execute the model in a simulation of the storage system (918) to generate a random read performance parameter for the storage system (918).
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公开(公告)号：US20240295993A1
公开(公告)日：2024-09-05
申请号：US18647677
申请日：2024-04-26
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer , Xinghui Duan , Massimo Zucchinali
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F2212/7202
Abstract: A computing system having a storage system that includes a storage device and a host device, where the host device is configured to issue memory access commands to the storage device. The computing system further includes a prediction system comprising processing circuitry that is configured to perform operations that cause the prediction system to identify one or more components of the storage system that limit random read performance of the storage system. The operations further cause the prediction system to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system. The operations additionally cause the prediction system to execute the model in a simulation of the storage system to generate a random read performance parameter for the storage system.
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Patent Agency Ranking
公开(公告)号：US20250028487A1
公开(公告)日：2025-01-23
申请号：US18906236
申请日：2024-10-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler L. Betz , Sundararajan N. Sankaranarayanan , Roberto Izzi , Massimo Zucchinali , Xiangyu Tang
IPC: G06F3/06
Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.
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公开(公告)号：US11989456B2
公开(公告)日：2024-05-21
申请号：US17771668
申请日：2019-12-31
Applicant: Micron Technology, Inc.
Inventor： David Aaron Palmer , Xinghui Duan , Massimo Zucchinali
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F12/0246 , G06F2212/7202
Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918). The operations additionally cause the prediction system (190) to execute the model in a simulation of the storage system (918) to generate a random read performance parameter for the storage system (918).
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公开(公告)号：US12124739B2
公开(公告)日：2024-10-22
申请号：US17949333
申请日：2022-09-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler L. Betz , Sundararajan N. Sankaranarayanan , Roberto Izzi , Massimo Zucchinali , Xiangyu Tang
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0634 , G06F3/0679
Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.
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公开(公告)号：US20240176549A1
公开(公告)日：2024-05-30
申请号：US18520387
申请日：2023-11-27
Applicant: Micron Technology, Inc.
Inventor： Roberto Izzi , Luca Porzio , Sean L. Manion , Massimo Zucchinali , Bryan D. Butler , Andrea Vigilante , Marco Onorato , Alfredo Palazzo
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0632 , G06F3/0674
Abstract: Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.
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公开(公告)号：US20240069809A1
公开(公告)日：2024-02-29
申请号：US17949333
申请日：2022-09-21
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler L. Betz , Sundararajan N. Sankaranarayanan , Roberto Izzi , Massimo Zucchinali , Xiangyu Tang
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0634 , G06F3/0679
Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.
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