公开(公告)号：US20250028487A1

公开(公告)日：2025-01-23

申请号：US18906236

申请日：2024-10-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler L. Betz ,  Sundararajan N. Sankaranarayanan ,  Roberto Izzi ,  Massimo Zucchinali ,  Xiangyu Tang

IPC: G06F3/06

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

公开(公告)号：US11955175B2

公开(公告)日：2024-04-09

申请号：US17729989

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Tecla Ghilardi ,  Violante Moschiano

IPC: G11C15/04 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C15/04 ,  G11C11/40615 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory system includes a memory device comprising a value data block a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key, identifies, from the plurality of stored search keys in a CAM block of a memory device, multiple redundant copies of a stored search key that match the input search key, and determines a plurality of locations in a value data block, the plurality of locations corresponding to the multiple redundant copies, wherein one of the plurality of locations comprises a first timestamp and data representing a value associated with the input search key, and wherein a remainder of the plurality of locations comprises one or more additional timestamps. The processing device further determines whether the first timestamp matches the one or more additional timestamps, and responsive to the first timestamp matching the one or more additional timestamps, retries from the one of the plurality of locations, the data representing the value associated with the input search key.

公开(公告)号：US20250046374A1

公开(公告)日：2025-02-06

申请号：US18915268

申请日：2024-10-14

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Manik Advani ,  Tomoko Ogura Iwasaki ,  Violante Moschiano

IPC: G11C15/04 ,  G11C7/10

Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key and identifies, from the plurality of stored search keys in the CAM block, multiple redundant copies of a stored search key that match the input search key. The processing device further determining whether a number of the multiple redundant copies of the stored search key that match the input search key satisfies a threshold criterion. Responsive to the number of the multiple redundant copies of the stored search key that match the input search key satisfying the threshold criterion, the processing device determines a match result for the input search key.

公开(公告)号：US11914474B2

公开(公告)日：2024-02-27

申请号：US18167992

申请日：2023-02-13

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Andrew M. Kowles ,  Adam J. Hieb

IPC: G06F11/07 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0772

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

公开(公告)号：US20230195572A1

公开(公告)日：2023-06-22

申请号：US18167992

申请日：2023-02-13

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Andrew M. Kowles ,  Adam J. Hieb

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0772

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

公开(公告)号：US20220375522A1

公开(公告)日：2022-11-24

申请号：US17729989

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Tecla Ghilardi ,  Violante Moschiano

IPC: G11C15/04 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory system includes a memory device comprising a value data block a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key, identifies, from the plurality of stored search keys in a CAM block of a memory device, multiple redundant copies of a stored search key that match the input search key, and determines a plurality of locations in a value data block, the plurality of locations corresponding to the multiple redundant copies, wherein one of the plurality of locations comprises a first timestamp and data representing a value associated with the input search key, and wherein a remainder of the plurality of locations comprises one or more additional timestamps. The processing device further determines whether the first timestamp matches the one or more additional timestamps, and responsive to the first timestamp matching the one or more additional timestamps, retries from the one of the plurality of locations, the data representing the value associated with the input search key.

公开(公告)号：US20220066868A1

公开(公告)日：2022-03-03

申请号：US16947975

申请日：2020-08-26

Applicant: Micron Technology Inc.

Inventor： Tyler L. Betz ,  Andrew M. Kowles ,  Adam J. Hieb

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: Disclosed is a system including a memory device having a plurality of physical memory segments and a processing device to perform operations that include, responsive to detecting a failure of a memory operation associated with a physical memory segment of the plurality of physical memory segments, quarantining the physical memory segment, responsive to quarantining the physical memory segment, performing one or more scanning operations on the physical memory segment, and determining, based on results of the one or more scanning operations, a viability status of the physical memory segment, wherein the viability status indicates an ability of the physical memory segment to store data.

公开(公告)号：US12142318B2

公开(公告)日：2024-11-12

申请号：US17729986

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Tyler L. Betz ,  Manik Advani ,  Tomoko Ogura Iwasaki ,  Violante Moschiano

IPC: G11C15/04 ,  G11C7/10

Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key and identifies, from the plurality of stored search keys in the CAM block, multiple redundant copies of a stored search key that match the input search key. The processing device further determining whether a number of the multiple redundant copies of the stored search key that match the input search key satisfies a threshold criterion. Responsive to the number of the multiple redundant copies of the stored search key that match the input search key satisfying the threshold criterion, the processing device determines a match result for the input search key.

公开(公告)号：US12124739B2

公开(公告)日：2024-10-22

申请号：US17949333

申请日：2022-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler L. Betz ,  Sundararajan N. Sankaranarayanan ,  Roberto Izzi ,  Massimo Zucchinali ,  Xiangyu Tang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

公开(公告)号：US20240069809A1

公开(公告)日：2024-02-29

申请号：US17949333

申请日：2022-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler L. Betz ,  Sundararajan N. Sankaranarayanan ,  Roberto Izzi ,  Massimo Zucchinali ,  Xiangyu Tang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.