公开(公告)号：US11269545B2

公开(公告)日：2022-03-08

申请号：US16075464

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Eric Kwok Fung Yuen ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi ,  Xinghui Duan ,  Giuseppe D'Eliseo

IPC: G06F3/06 ,  G06F12/02

Abstract: Devices and techniques for NAND logical-to-physical table region tracking are described herein. A write request, including a logical page and data to be written at the logical page, is received at a controller of a NAND device. The NAND controller may then establish an entry in a logical-to-physical (L2P) mapping table between the logical page and a physical page of a physical block of the NAND device to which the data is written. Here, the entry may be in a region of the L2P mapping table that is one of multiple regions. An indication of the region may be written in a data structure corresponding to the physical block.

公开(公告)号：US20200233606A1

公开(公告)日：2020-07-23

申请号：US16484066

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Eric Kwok Fung Yuen ,  Zhi Ping Yu ,  Guanzhong Wang

IPC: G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F1/10 ,  G06F1/324

Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to store requests to access the memory in the queue, determine whether queued memory access requests are to sequential addresses of the memory array or to random addresses of the memory array, reduce an operating rate of one or more first components of the memory control unit when the queued memory access requests are to sequential addresses of the memory array, and reduce an operating rate of one or more second components of the memory control unit when the queued memory access requests are to random addresses of the memory array.

公开(公告)号：US11620216B2

公开(公告)日：2023-04-04

申请号：US17750933

申请日：2022-05-23

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Guanzhong Wang ,  Xu Zhang ,  Eric Kwok Fung Yuen

IPC: G11C16/26 ,  G06F12/06 ,  G06F12/0893 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

公开(公告)号：US20220382453A1

公开(公告)日：2022-12-01

申请号：US17626713

申请日：2019-09-10

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan

IPC: G06F3/06

Abstract: Apparatus and methods are disclosed, including a sequential mapping table located within a flash memory array of a flash memory device. Selected examples include firmware in the flash memory device to load the sequential mapping table into a cache upon power and perform read and write operations using the sequential mapping table. Selected examples include firmware in the flash memory device to store an updated sequential mapping table into the flash memory array upon power down of the flash memory device.

公开(公告)号：US20220283939A1

公开(公告)日：2022-09-08

申请号：US17750933

申请日：2022-05-23

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Guan Zhong Wang ,  Xu Zhang ,  Eric Kwok Fung Yuen

IPC: G06F12/06 ,  G06F12/0893 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

公开(公告)号：US11341048B2

公开(公告)日：2022-05-24

申请号：US16488718

申请日：2018-10-29

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Guanzhong Wang ,  Xu Zhang ,  Eric Kwok Fung Yuen

IPC: G11C11/56 ,  G06F12/06 ,  G06F12/0893 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).

公开(公告)号：US20220011936A1

公开(公告)日：2022-01-13

申请号：US17486420

申请日：2021-09-27

Applicant: Micron Technology, Inc.

Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guanzhong Wang ,  Xinghui Duan ,  Hua Chen Li

IPC: G06F3/06 ,  G06F12/02

Abstract: Devices and techniques for variable width superblock addressing are described herein. A superblock width, specified in number of planes, is obtained. A superblock entry is created in a translation table of a NAND device. Here, the superblock entry may include a set of blocks, from the NAND device, that have the same block indexes across multiple die of the NAND device. The number of unique block indexes are equal to the number of planes and in different planes. A request, received from a requesting entityp, is performed using the superblock entry. Performing the request includes providing a single instruction to multiple die of the NAND device and multiple data segments. Here, a data segment corresponds to a block in the set of blocks specified by a tuple of block index and die. A result of the request is then returned to the requesting entity.

公开(公告)号：US20200142821A1

公开(公告)日：2020-05-07

申请号：US16075543

申请日：2017-12-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhao Cui ,  Eric Kwok Fung Yuen ,  Guan Zhong Wang ,  Xinghui Duan ,  Giuseppe D'Eliseo ,  Giuseppe Ferrari

IPC: G06F12/02 ,  G06F12/0873

Abstract: Devices and techniques for synchronizing NAND logical-to-physical table region tracking are described herein. Table region data structures for physical blocks are maintained. These structures include logical-to-physical (L2P) mapping table portions that point to the respective physical blocks. When garbage collection is performed on a block, table region structures for that block, and another (e.g., the next block to be garbage collected) are read to avoid loading L2P table regions that do not point to the block. If any of the read portions of the L2P table region fail to point to either the block or the other block, these L2P table portions are removed from the loaded table region data structures.

公开(公告)号：US10552316B2

公开(公告)日：2020-02-04

申请号：US16024380

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D'Eliseo ,  Luigi Esposito ,  Xinghui Duan ,  Lucia Santojanni ,  Massimo Iaculo

IPC: G06F12/02 ,  G11C16/10

Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.

公开(公告)号：US20240295993A1

公开(公告)日：2024-09-05

申请号：US18647677

申请日：2024-04-26

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Xinghui Duan ,  Massimo Zucchinali

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7202

Abstract: A computing system having a storage system that includes a storage device and a host device, where the host device is configured to issue memory access commands to the storage device. The computing system further includes a prediction system comprising processing circuitry that is configured to perform operations that cause the prediction system to identify one or more components of the storage system that limit random read performance of the storage system. The operations further cause the prediction system to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system. The operations additionally cause the prediction system to execute the model in a simulation of the storage system to generate a random read performance parameter for the storage system.