公开(公告)号：US11011234B1

公开(公告)日：2021-05-18

申请号：US16736029

申请日：2020-01-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yi-Ching Liu

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: The present disclosure relates to a non-volatile memory and operating method thereof. The non-volatile memory includes multiple memory strings, multiple bit switch units, a memory operation circuit and multiple source switch units. The bit switch units are electrically connected to the memory strings. The memory operation circuit is electrically connected to the bit switch units to transmit a write signal to the memory unit strings. The source switch units are electrically connected to the memory string so that the memory strings receive a bias signal via the source switch unit. In a program mode, when a first bit switch unit of the bit switch units is turned on and a first memory strings receives the write signal through the first bit switch unit, the source switch units electrically connected to the other memory strings will be turned on.

公开(公告)号：US10243454B2

公开(公告)日：2019-03-26

申请号：US15195732

申请日：2016-06-28

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Ting Hu ,  Shin-Jang Shen ,  Yi-Ching Liu

IPC: H03K5/003 ,  H02M3/07 ,  H03K3/356 ,  H03K5/05

Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

公开(公告)号：US09690650B2

公开(公告)日：2017-06-27

申请号：US13951130

申请日：2013-07-25

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Ching Liu ,  Chi Lo ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC: G11C29/00 ,  G06F11/10 ,  G11B20/18 ,  G11C7/10

CPC classification number: G06F11/1044 ,  G06F11/1008 ,  G06F11/1068 ,  G11B20/1833 ,  G11C7/1006

Abstract: A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations.

公开(公告)号：US09461623B2

公开(公告)日：2016-10-04

申请号：US14279004

申请日：2014-05-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsien-Hung Wu ,  Yi-Ching Liu ,  Shin-Jang Shen

IPC: H03K3/011 ,  H03K4/48 ,  H03B5/12 ,  H03K3/0231

CPC classification number: H03K3/011 ,  H03B5/1265 ,  H03K3/0231 ,  H03K4/48

Abstract: A method and a circuit for generating a clock signal from a clock integrated circuit are introduced herein. A compensation voltage is generated according to a temperature coefficient of a resistor and a clock period of a clock circuit, where the compensation voltage is resistor-corner independent. The clock period of the clock circuit is determined by the resistor and at least one capacitor of the clock circuit. The temperature dependence of the clock period of the clock circuit is reduced according to the compensation voltage.

Abstract translation: 这里介绍了用于从时钟集成电路产生时钟信号的方法和电路。 根据电阻的温度系数和时钟电路的时钟周期产生补偿电压，其中补偿电压为电阻 - 角独立。 时钟电路的时钟周期由电阻器和时钟电路的至少一个电容器确定。 根据补偿电压，时钟电路的时钟周期的温度依赖性降低。