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公开(公告)号：US06970389B2
公开(公告)日：2005-11-29
申请号：US10757594
申请日：2004-01-15
IPC分类号： G11C11/4097 , G11C7/02
CPC分类号： G11C11/4097 , G11C2207/005
摘要： An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.
摘要翻译： 集成存储器可以包括存储单元阵列，其具有用于选择存储器单元的字线，用于读出或写入存储器单元的数据信号的位线，以及连接到位线对的位线的读出放大器 位线对的末端。 在存储器访问期间的激活状态下，切换到位线对中的一个的至少一个可激活隔离电路可以隔离来自读出放大器更远离读出放大器的位线对的一部分。 结果，在存储器访问期间，可以显着地减少位线的有效电容。
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公开(公告)号：US07710810B2
公开(公告)日：2010-05-04
申请号：US11844047
申请日：2007-08-23
申请人： Manfred Proell , Stephan Schroeder
发明人： Manfred Proell , Stephan Schroeder
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/12 , G11C7/18 , G11C11/40618 , G11C11/40622 , G11C11/4094 , G11C11/4097
摘要： A device can be used for refreshing memory contents of first and second memory cells. The memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time. A pre-charge circuit is provided for bit lines for the first memory cells and the second memory cells. A controller may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.
摘要翻译： 可以使用设备来刷新第一和第二存储器单元的存储器内容。 在第一时间段内刷新第一存储器单元的存储器内容，并且在第二时间段内刷新第二存储器单元的存储器内容。 为第一存储器单元和第二存储单元的位线提供预充电电路。 控制器可以耦合到预充电电路以控制预充电电路，使得可以在第一时间段期间将预充电电压施加到第一存储器单元的位线，而不是在第二时段期间 并且可以在第二时间段期间而不是在第一时间段期间将预充电电压施加到第二存储器单元的位线。
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公开(公告)号：US20080056045A1
公开(公告)日：2008-03-06
申请号：US11844047
申请日：2007-08-23
申请人： Manfred Proell , Stephan Schroeder
发明人： Manfred Proell , Stephan Schroeder
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/12 , G11C7/18 , G11C11/40618 , G11C11/40622 , G11C11/4094 , G11C11/4097
摘要： A device is disclosed for refreshing memory contents of first and second memory cells, wherein the memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time, having a pre-charge circuit for bit lines for the first memory cells and the second memory cells, and having a controller which may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.
摘要翻译： 公开了一种用于刷新第一和第二存储器单元的存储器内容的装置，其中在第一时间段内刷新第一存储器单元的存储器内容，并且在第二时间段内刷新第二存储器单元的存储器内容， 具有用于第一存储器单元和第二存储器单元的位线的预充电电路，并且具有可以耦合到预充电电路以控制预充电电路的控制器，使得预充电电压可以是 在第一时间段期间而不是在第二时间段期间施加到第一存储器单元的位线，并且可以在第二时间段期间将预充电电压施加到第二存储器单元的位线;以及 不是在第一段时间。
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14.发明申请Memory and method for improving the reliability of a memory having a used memory region and an unused memory region 失效用于提高具有使用的存储器区域和未使用的存储器区域的存储器的可靠性的存储器和方法公开(公告)号：US20070133322A1
公开(公告)日：2007-06-14
申请号：US11541442
申请日：2006-09-29
申请人： Manfred Proell , Stephan Schroeder
发明人： Manfred Proell , Stephan Schroeder
CPC分类号： G11C29/24 , G11C29/88 , G11C29/883
摘要： A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory region can be substituted by functional memory elements in the unused memory region, having the steps of providing the used memory region with a first stress sequence; and providing the unused memory region with a second stress sequence.
摘要翻译： 一种用于提高具有使用的存储区域和未使用的存储器区域的存储器的可靠性的方法，其中所使用的存储器区域中的缺陷存储器元件可以由未使用的存储器区域中的功能存储元件代替，具有提供使用的存储器的步骤 具有第一应力序列的区域; 以及为第二应力序列提供未使用的存储区域。
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公开(公告)号：US20060056241A1
公开(公告)日：2006-03-16
申请号：US11225864
申请日：2005-09-13
CPC分类号： G11C29/50 , G11C2029/1204
摘要： An apparatus for aging a chip, comprising a first bit line connected to a first memory cell; a second bit line connected to a second memory cell; an access circuit for accessing the first memory cell via the first bit line and for accessing the second memory cell via the second bit line; a first controller for selectively connecting/disconnecting the first bit line to the access circuit and from the access circuit, respectively; a second controller for selectively connecting/disconnecting the second bit line to the access circuit and from the access circuit, respectively; a normal operating mode controller for controlling the first and second controller, wherein the normal operating mode controller is formed such to select the first controller in a normal operating mode for accessing the first memory cell, and to connect the access circuit to the first bit line, while the second controller is controlled to disconnect the access circuit from the second bit line; wherein the apparatus comprises: an aging mode controller for controlling the first and second controller, wherein the aging mode controller is formed to control the first controller and the second controller in an aging mode such that the access circuit is connected to the first and second bit lines for a predetermined time period.
摘要翻译： 一种用于老化芯片的装置，包括连接到第一存储器单元的第一位线; 连接到第二存储器单元的第二位线; 访问电路，用于经由所述第一位线访问所述第一存储器单元，以及经由所述第二位线访问所述第二存储器单元; 第一控制器，用于分别选择性地将第一位线连接到接入电路和接入电路; 第二控制器，用于分别选择性地将第二位线连接到接入电路和接入电路; 用于控制第一和第二控制器的正常操作模式控制器，其中形成正常操作模式控制器以便以正常操作模式选择第一控制器以访问第一存储器单元，并将访问电路连接到第一位线 同时控制第二控制器以将访问电路与第二位线断开; 其特征在于，所述装置包括：老化模式控制器，用于控制所述第一和第二控制器，其中所述老化模式控制器被形成为以老化模式控制所述第一控制器和所述第二控制器，使得所述存取电路连接到所述第一和第二位 线条预定时间段。
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公开(公告)号：US06914837B2
公开(公告)日：2005-07-05
申请号：US10761242
申请日：2004-01-22
IPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/005
摘要： A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as differential amplifiers. In an exemplary embodiment, a one of four bit line pairs of the two adjacent cell blocks can be selected for connection to a sense amplifier at any one time using respective isolation transistor pairs, in response to a connection control signal fed to the latter. A signal sent on a word line coupled to a memory cell associated with the selected bit line pair, provides access to the memory cell by the sense amplifier.
摘要翻译： 具有共享读出放大器结构的RAM存储器，其中读出放大器以两条相邻单元块之间的条带排列并被配置为差分放大器。 在示例性实施例中，响应于馈送给其的连接控制信号，可以选择两个相邻单元块的四个位线对中的一个，用于使用相应的隔离晶体管对在任何时间连接到读出放大器。 耦合到与所选位线对相关联的存储单元的字线上发送的信号通过读出放大器提供对存储单元的访问。
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17.发明授权Integrated semiconductor memory comprising at least one word line and method 有权集成半导体存储器，包括至少一个字线和方法公开(公告)号：US07206238B2
公开(公告)日：2007-04-17
申请号：US11218913
申请日：2005-09-01
CPC分类号： G11C29/50008 , G11C11/401 , G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.
摘要翻译： 半导体存储器和测试方法，用于在激活操作或去激活操作之后测试字线段（12）是否浮动。 为此，在字线段（12）发生电荷反转的情况下发生的充电反转电流（I）或馈送到字线（12）或导出的电荷量（Q） 由字线段（12）作为测量结果。 如果在字线段（12）激活或去激活时，测量的电荷反转电流（I）或相应的电荷量（Q）小于下限值，则确定相关字线段（ 12）有接触端子不良。 以这种方式，由此可以识别高阻抗或有缺陷的接触孔填充，并且可以用冗余字线替换相关联的字线段（12）。
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公开(公告)号：US20070047355A1
公开(公告)日：2007-03-01
申请号：US11467740
申请日：2006-08-28
IPC分类号： G11C7/02
CPC分类号： G11C11/4078 , G11C11/401 , G11C11/4091 , G11C11/4094 , G11C29/02 , G11C2029/1204 , G11C2029/5006 , G11C2207/005
摘要： A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time. The sense amplifier is short circuited with the bit line via the isolation transistor. The voltage on the bit line is collected by the sense amplifier, and compared with a reference voltage so as to detect the leakage current.
摘要翻译： 公开了一种用于检测半导体存储器的位线中的漏电流的方法。 在一个实施例中，该方法包括经由隔离晶体管将读出放大器与位线的连接隔离，将存储器单元读出到位线，等待直到经过预定的延迟时间，使得漏电流可测量地改变 延迟时间内位线上的电压。 读出放大器通过隔离晶体管与位线短路。 位线上的电压由读出放大器收集，并与参考电压进行比较，以便检测漏电流。
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19.发明授权公开(公告)号：US06906972B2
公开(公告)日：2005-06-14
申请号：US10733332
申请日：2003-12-12
IPC分类号： G11C7/10 , G11C11/4091 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C11/4091 , G11C11/4096 , G11C2207/002
摘要： An integrated semiconductor memory, and method for operating such a memory, in particular a DRAM memory, having local data lines (LDQT, LDQC) segmented in the column direction (Y), which local data lines can be connected by a CSL switch in response to a column select signal fed via a CSL line (CSL) running in the row direction (X) to primary sense amplifiers for transferring or accepting spread data signals to or from bit lines of the respective segment (I, II, III), LDQ switches are arranged at the interfaces between adjacent segments of the local data lines (LDQT, LDQC) for their connection to the local data lines (LDQT, LDQC) of adjacent segments (I, II, III). LDQ switches, depending on a control signal fed separately to each of said LDQ switches, are closed during a precharge phase, which takes place before each read cycle, of at least two adjacent LDQ segments.
摘要翻译： 集成半导体存储器和用于操作具有在列方向（Y）上分割的本地数据线（LDQT，LDQC）的这种存储器，特别是DRAM存储器的方法，该本地数据线可以通过CSL开关作为响应来连接 到通过在行方向（X）上运行的CSL线（CSL）馈送到主感测放大器的列选择信号，用于向或从相应段（I，II，III）的位线传送或接收扩展数据信号， 交换机被布置在本地数据线（LDQT，LDQC）的相邻段之间的接口处，用于连接到相邻段（I，II，III）的本地数据线（LDQT，LDQC）。 取决于分别馈送到每个所述LDQ开关的控制信号的LDQ开关在至少两个相邻的LDQ段之间的每个读取周期之前的预充电阶段期间被关闭。
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公开(公告)号：US20070260955A1
公开(公告)日：2007-11-08
申请号：US11677572
申请日：2007-02-21
申请人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers
发明人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers
IPC分类号： G01R31/28
CPC分类号： G11C29/36 , G11C2029/3602
摘要： Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied to a group of M data lines of the memory module, M being an integer.
摘要翻译： 将测试图案应用于存储器模块中的单元的方法和装置。 存储器模块中的测试辅助设备包含用于从至少两个基本M位测试模式中选择测试模式的测试模式选择设备。 测试图案被应用于存储器模块的M组数据线，M是整数。
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