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公开(公告)号：US06970389B2
公开(公告)日：2005-11-29
申请号：US10757594
申请日：2004-01-15
IPC分类号： G11C11/4097 , G11C7/02
CPC分类号： G11C11/4097 , G11C2207/005
摘要： An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.
摘要翻译： 集成存储器可以包括存储单元阵列，其具有用于选择存储器单元的字线，用于读出或写入存储器单元的数据信号的位线，以及连接到位线对的位线的读出放大器 位线对的末端。 在存储器访问期间的激活状态下，切换到位线对中的一个的至少一个可激活隔离电路可以隔离来自读出放大器更远离读出放大器的位线对的一部分。 结果，在存储器访问期间，可以显着地减少位线的有效电容。
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公开(公告)号：US06914837B2
公开(公告)日：2005-07-05
申请号：US10761242
申请日：2004-01-22
IPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/005
摘要： A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as differential amplifiers. In an exemplary embodiment, a one of four bit line pairs of the two adjacent cell blocks can be selected for connection to a sense amplifier at any one time using respective isolation transistor pairs, in response to a connection control signal fed to the latter. A signal sent on a word line coupled to a memory cell associated with the selected bit line pair, provides access to the memory cell by the sense amplifier.
摘要翻译： 具有共享读出放大器结构的RAM存储器，其中读出放大器以两条相邻单元块之间的条带排列并被配置为差分放大器。 在示例性实施例中，响应于馈送给其的连接控制信号，可以选择两个相邻单元块的四个位线对中的一个，用于使用相应的隔离晶体管对在任何时间连接到读出放大器。 耦合到与所选位线对相关联的存储单元的字线上发送的信号通过读出放大器提供对存储单元的访问。
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3.发明授权Integrated semiconductor memory and method for operating an integrated semiconductor memory 有权用于操作集成半导体存储器的集成半导体存储器和方法公开(公告)号：US07248536B2
公开(公告)日：2007-07-24
申请号：US11245455
申请日：2005-10-06
IPC分类号： G11C8/00
CPC分类号： G11C29/025 , G11C7/18 , G11C8/08 , G11C11/401 , G11C11/4085 , G11C11/4097 , G11C29/02 , G11C2029/1202
摘要： A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation. It can thereby be ascertained which of two switching elements (16, 17) of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment (12).
摘要翻译： 至少以测试方式，提供半导体存储器和用于依次操作的方法，以不经由用于去激活的第一行（21）去激活分段字线的字线段（12），而是 经由第二行（22）经由字线段（12）被另外激活。 第二行（22）可以可选地被提供用于激活或第三电位（Vgnd）的第二电位（Vpp）偏置。 如果第三电位（Vgnd）用于至少暂时禁用字线段（12），则可以经由将字线段耦合到第二线路（22）的开关元件（17）来驱动字线段， ，而驱动器段（20）的互补开关元件（16）必须用于去激活。 因此，可以确定驱动器段的两个开关元件（16,17）中的哪一个有缺陷，以及由于浮动电位的永久替换字线，半导体存储器是否以没有错误的方式起作用 经测试的字线段（12）。
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4.发明授权Integrated semiconductor memory comprising at least one word line and method 有权集成半导体存储器，包括至少一个字线和方法公开(公告)号：US07206238B2
公开(公告)日：2007-04-17
申请号：US11218913
申请日：2005-09-01
CPC分类号： G11C29/50008 , G11C11/401 , G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.
摘要翻译： 半导体存储器和测试方法，用于在激活操作或去激活操作之后测试字线段（12）是否浮动。 为此，在字线段（12）发生电荷反转的情况下发生的充电反转电流（I）或馈送到字线（12）或导出的电荷量（Q） 由字线段（12）作为测量结果。 如果在字线段（12）激活或去激活时，测量的电荷反转电流（I）或相应的电荷量（Q）小于下限值，则确定相关字线段（ 12）有接触端子不良。 以这种方式，由此可以识别高阻抗或有缺陷的接触孔填充，并且可以用冗余字线替换相关联的字线段（12）。
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公开(公告)号：US20070047355A1
公开(公告)日：2007-03-01
申请号：US11467740
申请日：2006-08-28
IPC分类号： G11C7/02
CPC分类号： G11C11/4078 , G11C11/401 , G11C11/4091 , G11C11/4094 , G11C29/02 , G11C2029/1204 , G11C2029/5006 , G11C2207/005
摘要： A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time. The sense amplifier is short circuited with the bit line via the isolation transistor. The voltage on the bit line is collected by the sense amplifier, and compared with a reference voltage so as to detect the leakage current.
摘要翻译： 公开了一种用于检测半导体存储器的位线中的漏电流的方法。 在一个实施例中，该方法包括经由隔离晶体管将读出放大器与位线的连接隔离，将存储器单元读出到位线，等待直到经过预定的延迟时间，使得漏电流可测量地改变 延迟时间内位线上的电压。 读出放大器通过隔离晶体管与位线短路。 位线上的电压由读出放大器收集，并与参考电压进行比较，以便检测漏电流。
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6.发明申请Integrated semiconductor memory and method for operating an integrated semiconductor memory 有权用于操作集成半导体存储器的集成半导体存储器和方法公开(公告)号：US20060083100A1
公开(公告)日：2006-04-20
申请号：US11245455
申请日：2005-10-06
IPC分类号： G11C8/00
CPC分类号： G11C29/025 , G11C7/18 , G11C8/08 , G11C11/401 , G11C11/4085 , G11C11/4097 , G11C29/02 , G11C2029/1202
摘要： A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation. It can thereby be ascertained which of two switching elements (16, 17) of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment (12).
摘要翻译： 至少以测试方式，提供半导体存储器和用于依次操作的方法，以不经由用于去激活的第一行（21）去激活分段字线的字线段（12），而是 经由第二行（22）经由字线段（12）被另外激活。 第二行（22）可以可选地被提供用于激活或第三电位（Vgnd）的第二电位（Vpp）偏置。 如果第三电位（Vgnd）用于至少暂时禁用字线段（12），则可以经由将字线段耦合到第二线路（22）的开关元件（17）来驱动字线段， ，而驱动器段（20）的互补开关元件（16）必须用于去激活。 因此，可以确定驱动器段的两个开关元件（16,17）中的哪一个有缺陷，以及由于浮动电位的永久替换字线，半导体存储器是否以没有错误的方式起作用 经测试的字线段（12）。
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7.发明申请Integrated semiconductor memory comprising at least one word line and method 有权集成半导体存储器，包括至少一个字线和方法公开(公告)号：US20060056266A1
公开(公告)日：2006-03-16
申请号：US11218913
申请日：2005-09-01
CPC分类号： G11C29/50008 , G11C11/401 , G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A semiconductor memory and a test method for testing whether word line segments (12) are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment (12) being subjected to charge reversal or a charge quantity (Q) which is fed to the word line (12) or conducted away from the word line segment (12) as a result of this is measured. If, upon activation or deactivation of a word line segment (12), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment (12) has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments (12) can be replaced by redundant word lines.
摘要翻译： 半导体存储器和测试方法，用于在激活操作或去激活操作之后测试字线段（12）是否浮动。 为此，在字线段（12）发生电荷反转的情况下发生的充电反转电流（I）或馈送到字线（12）或导出的电荷量（Q） 由字线段（12）作为测量结果。 如果在字线段（12）激活或去激活时，测量的电荷反转电流（I）或相应的电荷量（Q）小于下限值，则确定相关字线段（ 12）有接触端子不良。 以这种方式，由此可以识别高阻抗或有缺陷的接触孔填充，并且可以用冗余字线替换相关联的字线段（12）。
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8.发明申请公开(公告)号：US20050057982A1
公开(公告)日：2005-03-17
申请号：US10911230
申请日：2004-08-04
IPC分类号： G11C8/08 , G11C11/406 , G11C11/408 , H03L7/00
CPC分类号： G11C7/04 , G11C8/08 , G11C11/406 , G11C11/4085 , G11C2211/4068
摘要： A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.
摘要翻译： 半导体存储器包括具有存储电容器的存储单元（2）和具有电极的晶体管，该电极可与两个不同的电位（V1，V2）电偏置，以便打开和闭合晶体管。 用于晶体管截止状态的电极电位（V2）是依赖于温度的电位，其值由半导体存储器（1）温度控制，使得第二电位（V2）变得更加不同于 随着温度（T）的第一电位（V1）增加。
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9.发明授权公开(公告)号：US07120074B2
公开(公告)日：2006-10-10
申请号：US10911230
申请日：2004-08-04
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C8/08 , G11C11/406 , G11C11/4085 , G11C2211/4068
摘要： A semiconductor memory includes storage cells (2) that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (V1, V2) in order to open and close the transistor. The electrode potential (V2) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory (1) so that the second electrical potential (V2) becomes more different from the first electrical potential (V1) as the temperature (T) increases.
摘要翻译： 半导体存储器包括具有存储电容器的存储单元（2）和具有电极的晶体管，该电极可与两个不同的电位（V 1，V 2）电偏置，以便打开和闭合晶体管。 用于晶体管截止状态的电极电位（V 2）是依赖于温度的温度的电位，其值由半导体存储器（1）温度控制，使得第二电位（V 2）变得更大 与温度（T）增加时不同于第一电位（V 1）。
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10.发明授权Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs 有权用于使用用于多个输入和输出的公共节点来测试存储器芯片的方法和装置公开(公告)号：US07877649B2
公开(公告)日：2011-01-25
申请号：US11934644
申请日：2007-11-02
申请人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
发明人： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers , Wolfgang Ruf , Hermann Hass
IPC分类号： G11C29/00
CPC分类号： G11C29/40 , G11C29/1201 , G11C29/26 , G11C29/48 , G11C29/56 , G11C2029/2602 , G11C2029/5602
摘要： An apparatus and methods for testing an integrated device comprising memory a test device are provided. At least two data inputs of the memory are coupled to a data output of the test device. As an alternative, at least two data outputs of the memory are coupled to a data input of the test device. Test data are transferred from the test device to the memory chip and written to memory cells of the memory. Data are read from the memory cells of the memory and transferring from the memory to the test device. The data read from the memory chip are compared with the test data written to the memory in order to identify faults of the memory.
摘要翻译： 提供一种用于测试包括存储器的测试装置的集成装置的装置和方法。 存储器的至少两个数据输入耦合到测试设备的数据输出。 作为替代，存储器的至少两个数据输出耦合到测试设备的数据输入。 测试数据从测试设备传输到存储器芯片并写入存储器的存储单元。 从存储器的存储单元读取数据并从存储器传送到测试设备。 将从存储器芯片读取的数据与写入存储器的测试数据进行比较，以识别存储器的故障。
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