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公开(公告)号：US09937009B2
公开(公告)日：2018-04-10
申请号：US14387333
申请日：2012-03-30
Applicant: Stephan Schroeder , Kevin Soldan
Inventor： Stephan Schroeder , Kevin Soldan
CPC classification number: A61B90/03 , A61B17/1622 , A61B17/1624 , A61B17/8875 , A61B2017/00482 , A61B2090/031 , A61B2090/037 , A61C1/186 , F16D9/10
Abstract: A torque-limiting assembly for a surgical powertool has an input shaft and an output shaft. Two relatively rotatable parts of the assembly are configured to be locked against relative rotation by at least one shearable piece for torque transfer between the input shaft and the output shaft up to a torque limit. The assembly further comprises at least one shear off structure rotationally fixed to one of the two relatively rotatable parts for shearing off a portion of the at least one shearable piece above the torque limit so as to unlock the two relatively rotatable parts for relative rotation.
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公开(公告)号：US07710810B2
公开(公告)日：2010-05-04
申请号：US11844047
申请日：2007-08-23
Applicant: Manfred Proell , Stephan Schroeder
Inventor： Manfred Proell , Stephan Schroeder
IPC: G11C7/00
CPC classification number: G11C11/406 , G11C7/12 , G11C7/18 , G11C11/40618 , G11C11/40622 , G11C11/4094 , G11C11/4097
Abstract: A device can be used for refreshing memory contents of first and second memory cells. The memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time. A pre-charge circuit is provided for bit lines for the first memory cells and the second memory cells. A controller may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.
Abstract translation: 可以使用设备来刷新第一和第二存储器单元的存储器内容。 在第一时间段内刷新第一存储器单元的存储器内容，并且在第二时间段内刷新第二存储器单元的存储器内容。 为第一存储器单元和第二存储单元的位线提供预充电电路。 控制器可以耦合到预充电电路以控制预充电电路，使得可以在第一时间段期间将预充电电压施加到第一存储器单元的位线，而不是在第二时段期间 并且可以在第二时间段期间而不是在第一时间段期间将预充电电压施加到第二存储器单元的位线。
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公开(公告)号：US20080056045A1
公开(公告)日：2008-03-06
申请号：US11844047
申请日：2007-08-23
Applicant: Manfred Proell , Stephan Schroeder
Inventor： Manfred Proell , Stephan Schroeder
IPC: G11C7/00
CPC classification number: G11C11/406 , G11C7/12 , G11C7/18 , G11C11/40618 , G11C11/40622 , G11C11/4094 , G11C11/4097
Abstract: A device is disclosed for refreshing memory contents of first and second memory cells, wherein the memory contents of the first memory cells are refreshed in a first period of time and the memory contents of the second memory cells are refreshed in a second period of time, having a pre-charge circuit for bit lines for the first memory cells and the second memory cells, and having a controller which may be coupled to the pre-charge circuit to control the pre-charge circuit such that a pre-charge voltage may be applied to the bit lines of the first memory cells during the first period of time and not during the second period of time and that the pre-charge voltage may be applied to the bit lines of the second memory cells during the second period of time and not during the first period of time.
Abstract translation: 公开了一种用于刷新第一和第二存储器单元的存储器内容的装置，其中在第一时间段内刷新第一存储器单元的存储器内容，并且在第二时间段内刷新第二存储器单元的存储器内容， 具有用于第一存储器单元和第二存储器单元的位线的预充电电路，并且具有可以耦合到预充电电路以控制预充电电路的控制器，使得预充电电压可以是 在第一时间段期间而不是在第二时间段期间施加到第一存储器单元的位线，并且可以在第二时间段期间将预充电电压施加到第二存储器单元的位线;以及 不是在第一段时间。
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4.发明申请Memory and method for improving the reliability of a memory having a used memory region and an unused memory region 失效用于提高具有使用的存储器区域和未使用的存储器区域的存储器的可靠性的存储器和方法公开(公告)号：US20070133322A1
公开(公告)日：2007-06-14
申请号：US11541442
申请日：2006-09-29
Applicant: Manfred Proell , Stephan Schroeder
Inventor： Manfred Proell , Stephan Schroeder
CPC classification number: G11C29/24 , G11C29/88 , G11C29/883
Abstract: A method for improving the reliability of a memory having a used memory region and an unused memory region, wherein defect memory elements in the used memory region can be substituted by functional memory elements in the unused memory region, having the steps of providing the used memory region with a first stress sequence; and providing the unused memory region with a second stress sequence.
Abstract translation: 一种用于提高具有使用的存储区域和未使用的存储器区域的存储器的可靠性的方法，其中所使用的存储器区域中的缺陷存储器元件可以由未使用的存储器区域中的功能存储元件代替，具有提供使用的存储器的步骤 具有第一应力序列的区域; 以及为第二应力序列提供未使用的存储区域。
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公开(公告)号：US20060056241A1
公开(公告)日：2006-03-16
申请号：US11225864
申请日：2005-09-13
Applicant: Juergen Auge , Helmut Fischer , Manfred Proell , Stephan Schroeder
Inventor： Juergen Auge , Helmut Fischer , Manfred Proell , Stephan Schroeder
CPC classification number: G11C29/50 , G11C2029/1204
Abstract: An apparatus for aging a chip, comprising a first bit line connected to a first memory cell; a second bit line connected to a second memory cell; an access circuit for accessing the first memory cell via the first bit line and for accessing the second memory cell via the second bit line; a first controller for selectively connecting/disconnecting the first bit line to the access circuit and from the access circuit, respectively; a second controller for selectively connecting/disconnecting the second bit line to the access circuit and from the access circuit, respectively; a normal operating mode controller for controlling the first and second controller, wherein the normal operating mode controller is formed such to select the first controller in a normal operating mode for accessing the first memory cell, and to connect the access circuit to the first bit line, while the second controller is controlled to disconnect the access circuit from the second bit line; wherein the apparatus comprises: an aging mode controller for controlling the first and second controller, wherein the aging mode controller is formed to control the first controller and the second controller in an aging mode such that the access circuit is connected to the first and second bit lines for a predetermined time period.
Abstract translation: 一种用于老化芯片的装置，包括连接到第一存储器单元的第一位线; 连接到第二存储器单元的第二位线; 访问电路，用于经由所述第一位线访问所述第一存储器单元，以及经由所述第二位线访问所述第二存储器单元; 第一控制器，用于分别选择性地将第一位线连接到接入电路和接入电路; 第二控制器，用于分别选择性地将第二位线连接到接入电路和接入电路; 用于控制第一和第二控制器的正常操作模式控制器，其中形成正常操作模式控制器以便以正常操作模式选择第一控制器以访问第一存储器单元，并将访问电路连接到第一位线 同时控制第二控制器以将访问电路与第二位线断开; 其特征在于，所述装置包括：老化模式控制器，用于控制所述第一和第二控制器，其中所述老化模式控制器被形成为以老化模式控制所述第一控制器和所述第二控制器，使得所述存取电路连接到所述第一和第二位 线条预定时间段。
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Patent Agency Ranking
公开(公告)号：US06914837B2
公开(公告)日：2005-07-05
申请号：US10761242
申请日：2004-01-22
Applicant: Stephan Schroeder , Manfred Proell , Aurel Von Campenhausen , Marcin Gnat
Inventor： Stephan Schroeder , Manfred Proell , Aurel Von Campenhausen , Marcin Gnat
IPC: G11C7/06 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C7/00
CPC classification number: G11C7/06 , G11C7/12 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/005
Abstract: A RAM memory with a shared sense amplifier structure, in which sense amplifiers are arranged in strips between two adjacent cell blocks and are configured as differential amplifiers. In an exemplary embodiment, a one of four bit line pairs of the two adjacent cell blocks can be selected for connection to a sense amplifier at any one time using respective isolation transistor pairs, in response to a connection control signal fed to the latter. A signal sent on a word line coupled to a memory cell associated with the selected bit line pair, provides access to the memory cell by the sense amplifier.
Abstract translation: 具有共享读出放大器结构的RAM存储器，其中读出放大器以两条相邻单元块之间的条带排列并被配置为差分放大器。 在示例性实施例中，响应于馈送给其的连接控制信号，可以选择两个相邻单元块的四个位线对中的一个，用于使用相应的隔离晶体管对在任何时间连接到读出放大器。 耦合到与所选位线对相关联的存储单元的字线上发送的信号通过读出放大器提供对存储单元的访问。
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公开(公告)号：US20150148176A1
公开(公告)日：2015-05-28
申请号：US14387333
申请日：2012-03-30
Applicant: Stephan Schroeder , Kevin Soldan
Inventor： Stephan Schroeder , Kevin Soldan
CPC classification number: A61B90/03 , A61B17/1622 , A61B17/1624 , A61B17/8875 , A61B2017/00482 , A61B2090/031 , A61B2090/037 , A61C1/186 , F16D9/10
Abstract: A torque-limiting assembly for a surgical powertool has an input shaft and an output shaft. Two relatively rotatable parts of the assembly are configured to be locked against relative rotation by at least one shearable piece for torque transfer between the input shaft and the output shaft up to a torque limit. The assembly further comprises at least one shear off structure rotationally fixed to one of the two relatively rotatable parts for shearing off a portion of the at least one shearable piece above the torque limit so as to unlock the two relatively rotatable parts for relative rotation.
Abstract translation: 用于外科手术工具的转矩限制组件具有输入轴和输出轴。 组件的两个相对可旋转的部件构造成通过至少一个可剪切件锁定在相对旋转之间，用于在输入轴和输出轴之间转矩直到扭矩极限。 组件还包括至少一个剪切结构，其旋转地固定到两个相对可旋转的部分中的一个，用于剪切所述至少一个可剪切件的一部分高于扭矩极限，以便解锁两个相对可旋转的部件以进行相对旋转。
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8.发明授权Integrated device for simplified parallel testing, test board for testing a plurality of integrated devices, and test system and tester unit 失效用于简化并行测试的集成设备，用于测试多个集成设备的测试板，以及测试系统和测试仪单元公开(公告)号：US07752510B2
公开(公告)日：2010-07-06
申请号：US11684533
申请日：2007-03-09
Applicant: Manfred Proell , Stephan Schroeder , Wolfgang Ruf , Hermann Haas
Inventor： Manfred Proell , Stephan Schroeder , Wolfgang Ruf , Hermann Haas
CPC classification number: G01R31/3172 , G01R31/31926 , G01R31/31935
Abstract: An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to an output signal. The register element is connected to a data input of the integrated device in order to accept a data item, which is applied to the data input, responsive to the output signal.
Abstract translation: 集成装置包括功能电路，用于测试功能电路并提供错误数据项的测试电路和用于存储错误数据项的寄存器元件，并用于在集成器件的错误数据输出端输出错误数据项 到输出信号。 寄存器元件连接到集成器件的数据输入，以便响应于输出信号接受应用于数据输入的数据项。
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公开(公告)号：US07402859B2
公开(公告)日：2008-07-22
申请号：US11079884
申请日：2005-03-15
Applicant: Joerg Vollrath , Marcin Gnat , Ralf Schneider , Stephan Schroeder
Inventor： Joerg Vollrath , Marcin Gnat , Ralf Schneider , Stephan Schroeder
IPC: H01L27/108 , H01L21/336
CPC classification number: H01L29/78696 , H01L27/10867 , H01L27/10873 , H01L29/0649 , H01L29/1037 , H01L29/42384 , H01L29/66757 , H01L29/66772 , H01L29/78606 , H01L29/78618
Abstract: A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the first semiconductor region and the second semiconductor region, a semiconductor strip on the surface of the semiconductor layer, which semiconductor strip overlaps the first semiconductor region and the second semiconductor region and adjoins these. A gate overlaps the semiconductor strip at least in the region of the insulating layer. A gate dielectric insulates the gate from the semiconductor strip the first semiconductor region and the second semiconductor region. The semiconductor strip and the gate being formed such that the semiconductor strip is electrically insulating at a first predetermined gate voltage and is electrically conductive at a second predetermined gate voltagero.
Abstract translation: 场效应半导体包括在半导体层的表面上彼此相邻布置的半导体层中具有表面的第一和第二半导体区域的半导体层，在第一半导体区域和第二半导体区域之间的绝缘层 半导体区域，半导体层的表面上的半导体条，该半导体条与第一半导体区域和第二半导体区域重叠，并与其邻接。 至少在绝缘层的区域中，栅极与半导体条重叠。 栅介质将栅极与半导体条绝缘在第一半导体区和第二半导体区之间。 半导体条和栅极形成为使得半导体条以第一预定栅极电压电绝缘并且在第二预定栅极电压下导电。
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公开(公告)号：US20070260955A1
公开(公告)日：2007-11-08
申请号：US11677572
申请日：2007-02-21
Applicant: Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers
Inventor： Joerg Kliewer , Manfred Proell , Stephan Schroeder , Georg Eggers
IPC: G01R31/28
CPC classification number: G11C29/36 , G11C2029/3602
Abstract: Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied to a group of M data lines of the memory module, M being an integer.
Abstract translation: 将测试图案应用于存储器模块中的单元的方法和装置。 存储器模块中的测试辅助设备包含用于从至少两个基本M位测试模式中选择测试模式的测试模式选择设备。 测试图案被应用于存储器模块的M组数据线，M是整数。
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