公开(公告)号：US4529305A

公开(公告)日：1985-07-16

申请号：US395245

申请日：1982-07-06

申请人： Walter T. Welford ,  Andrew D. G. Stewart ,  John S. Dodson

发明人： Walter T. Welford ,  Andrew D. G. Stewart ,  John S. Dodson

IPC分类号： G01N21/87

CPC分类号： G01N21/87

摘要： Method and apparatus for examining a gemstone to determine a parameter thereof. A thin beam of light is projected onto the stone, the beam is moved relative to the stone, the position where the beam strikes the stone is sensed in a direction different from that in which the beam is projected, and a parameter is determined making use of information derived from such sensing.

摘要翻译： 用于检查宝石以确定其参数的方法和装置。 光束投射到石头上，光束相对于石头移动，光束撞击石头的位置在与投影光束不同的方向上被感测，并且确定使用参数 从这种感知得到的信息。

公开(公告)号：US08775906B2

公开(公告)日：2014-07-08

申请号：US13611909

申请日：2012-09-12

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

IPC分类号： G11C29/42 ,  G06F11/10 ,  G11C29/54 ,  G11C29/04

CPC分类号： G06F11/1076 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0895 ,  G11C2029/0411

摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

公开(公告)号：US20130151929A1

公开(公告)日：2013-06-13

申请号：US13313364

申请日：2011-12-07

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

IPC分类号： G06F11/16 ,  G06F12/08

CPC分类号： G06F11/1076 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0895 ,  G11C2029/0411

摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

摘要翻译： 提供了用于在系统存储器内有效存储元位的机制。 这些机制将L / G位和SUE位组合以形成元位。 机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。 这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。 这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。 机制执行错误处理，而不管请求是否在全球重新发布。

公开(公告)号：US20130111103A1

公开(公告)日：2013-05-02

申请号：US13283956

申请日：2011-10-28

申请人： John S. Dodson ,  Randal C. Swanberg

发明人： John S. Dodson ,  Randal C. Swanberg

IPC分类号： G06F12/02 ,  G06F12/16 ,  G06F12/06

CPC分类号： G06F12/0246 ,  G06F2212/7202

摘要： A memory configured to provide a write requestor with a direct write programming interface to a disk device. A first persistent memory is configured for designating at least a portion its memory locations as central processing unit (CPU) load storable memory. The first persistent memory is also configured for receiving write data from the write requestor, for storing the write data in the CPU load storable memory, and for returning a write completion message to the write requestor in response to the storing completing. The memory also includes a second persistent memory that includes the disk device, and a controller in communication with the first and second persistent memories. The controller is configured for detecting the storing of the write data to the CPU load storable memory and for copying the write data to the second persistent memory in response to detecting the storing of the write data.

摘要翻译： 配置用于向写请求者提供与盘设备的直接写入编程接口的存储器。 第一持久存储器被配置为将其存储器位置的至少一部分指定为中央处理单元（CPU）加载可存储存储器。 第一持久存储器还被配置为从写入请求器接收写入数据，用于将写入数据存储在CPU可加载存储器中，并且响应于存储完成而将写入完成消息返回到写入请求者。 存储器还包括包括磁盘设备的第二持久存储器以及与第一和第二持久存储器通信的控制器。 控制器被配置为响应于检测到写入数据的存储而检测写入数据到CPU负载可存储存储器的存储器并将写入数据复制到第二持久存储器。

公开(公告)号：US5623694A

公开(公告)日：1997-04-22

申请号：US316978

申请日：1994-10-03

申请人： Ravi K. Arimilli ,  John S. Dodson ,  Jerry D. Lewis

发明人： Ravi K. Arimilli ,  John S. Dodson ,  Jerry D. Lewis

IPC分类号： G06F13/00 ,  G06F11/14 ,  G06F13/40

CPC分类号： G06F13/4054 ,  G06F11/1407

摘要： A data processing system includes one or more processing units, a memory subsystem, and one or more input/output channel controllers, wherein each of the input/output channel controllers include the capability of speculative input/output execution. The speculative I/O execution technique according to the present invention may include several options. The speculative execution in the IOCC begins after receiving a raw address even though the operation can still be remotely retried. The programmed I/O latency time is reduced significantly due to the early speculative commencement of the IOCC operation. The IOCC may have to abort the speculative operation if a remote flow control retry is received. If, however, no retry is received then significant time is saved because the speculative operation proceeds.

摘要翻译： 数据处理系统包括一个或多个处理单元，存储器子系统和一个或多个输入/输出通道控制器，其中每个输入/输出通道控制器包括投机输入/输出执行的能力。 根据本发明的推测性I / O执行技术可以包括若干选项。 即使该操作仍可远程重试，IOCC的投机执行在收到原始地址后开始。 由于IOCC运营的早期投机开始，编程的I / O延迟时间显着降低。 如果接收到远程流量控制重试，IOCC可能必须中止推测操作。 然而，如果没有收到重试，那么由于投机操作进行而节省了大量时间。

公开(公告)号：US08775904B2

公开(公告)日：2014-07-08

申请号：US13313364

申请日：2011-12-07

申请人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

发明人： John S. Dodson ,  Benjiman L. Goodman ,  Steven J. Hnatko ,  Kenneth L. Wright

IPC分类号： G11C29/42 ,  G06F11/10 ,  G11C29/54 ,  G11C29/04

CPC分类号： G06F11/1076 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0895 ,  G11C2029/0411

摘要： Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally.

摘要翻译： 提供了用于在系统存储器内有效存储元位的机制。 这些机制将L / G位和SUE位组合以形成元位。 机制然后在第一个数据周期上确定高速缓存行的本地/全局状态。 这些机制将数据转发到请求的高速缓存，并且请求高速缓存可以基于高速缓存行的本地/全局状态全局重新发出请求。 这些机制然后在数据的第二个或随后的周期中确定高速缓存行的特殊的不可校正错误状态。 机制执行错误处理，而不管请求是否在全球重新发布。

公开(公告)号：US5548797A

公开(公告)日：1996-08-20

申请号：US316976

申请日：1994-10-03

申请人： Ravi K. Arimilli ,  John S. Dodson ,  Jerry D. Lewis

发明人： Ravi K. Arimilli ,  John S. Dodson ,  Jerry D. Lewis

IPC分类号： G06F13/12 ,  G06F1/06 ,  G06F1/10 ,  G06F9/38 ,  G06F13/42 ,  H03K5/15 ,  G06F1/04 ,  G06F13/14

CPC分类号： G06F9/3869 ,  H03K5/15026

摘要： An input/output channel controller includes a storage array for temporarily storing data and multiple clocks to access or update the data. One or more array clock signals are generated from a system clock combined with other clock signals to generate a single clock signal which is positioned in time by a clock positioning circuit to accommodate circuit throughput delay variations and to effectively reduce hold time to zero. Storage arrays may be clocked at significantly higher frequencies and arrays may have multiple gated clocks without incurring the hold time problems.

摘要翻译： 输入/输出通道控制器包括用于临时存储数据的存储阵列和用于访问或更新数据的多个时钟。 一个或多个阵列时钟信号从与其它时钟信号组合的系统时钟产生，以产生单个时钟信号，时钟信号由时钟定位电路定时，以适应电路吞吐量延迟变化并有效地将保持时间减少到零。 存储阵列可以以显着更高的频率进行计时，并且阵列可以具有多个门控时钟，而不会导致保持时间问题。

公开(公告)号：US20130297879A1

公开(公告)日：2013-11-07

申请号：US13460873

申请日：2012-05-01

申请人： Bulent Abali ,  John S. Dodson ,  Moinuddin K. Qureshi ,  Balaram Sinharoy

发明人： Bulent Abali ,  John S. Dodson ,  Moinuddin K. Qureshi ,  Balaram Sinharoy

IPC分类号： G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/0873 ,  G06F12/0895 ,  G06F12/121 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/313 ,  G06F2212/6032 ,  G06F2212/6082

摘要： A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)—way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.

摘要翻译： 称为概率集关联缓存（PAC）的计算机高速缓冲存储器组织具有直接映射高速缓存的硬件复杂性和延迟，但在一小部分时间内用作集合关联高速缓存，从而比直接映射高速缓存命中率更好。 该组织被认为是（1 + P）组合关联高速缓存，其中所选择的参数“覆盖概率P”决定了平均关联性，例如，对于P = 0.1，其实际上它像1.1路组合关联高速缓存一样运行。

公开(公告)号：US5613153A

公开(公告)日：1997-03-18

申请号：US316977

申请日：1994-10-03

申请人： Ravi K. Arimilli ,  John S. Dodson ,  Guy L. Guthrie ,  Jerry D. Lewis

发明人： Ravi K. Arimilli ,  John S. Dodson ,  Guy L. Guthrie ,  Jerry D. Lewis

IPC分类号： G06F12/08 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40 ,  G06F15/16 ,  G06F15/177 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0835 ,  G06F13/28 ,  G06F13/405 ,  G06F13/4059

摘要： An I/O channel controller implements coherency and synchronization mechanisms, which allow the I/O channel controller to provide fully coherent direct memory access operations on a multiprocessor system bus, without implementing a retry protocol. This is made possible by performing delayed cache invalidates for real-time cache coherency conflicts between processors and I/O devices. Furthermore, I/O DMA writes occur real-time to the memory system and without the traditional Read With Intent to Modify (RWITM) operations. Completion of PIO operations has been coupled to the completion of I/O DMA writes operations in order to provide "seamless" I/O synchronization with respect to processor execution. An IOCC implementation has been described which benefits from those techniques by significantly reducing design complexity.

摘要翻译： I / O通道控制器实现一致性和同步机制，允许I / O通道控制器在多处理器系统总线上提供完全相干的直接存储器访问操作，而不需要重试协议。 这可以通过对处理器和I / O设备之间的实时高速缓存一致性冲突执行延迟缓存无效。 此外，I / O DMA写入会实时发生到存储器系统，而不需要传统的Read With Intent to Modify（RWITM）操作。 完成PIO操作已经与完成I / O DMA写入操作相结合，以便为处理器执行提供“无缝”I / O同步。 已经描述了IOCC实现，其通过显着降低设计复杂性而受益于这些技术。

公开(公告)号：US4417564A

公开(公告)日：1983-11-29

申请号：US269271

申请日：1981-06-01

申请人： John C. Lawrence ,  Andrew D. G. Stewart ,  John S. Dodson

发明人： John C. Lawrence ,  Andrew D. G. Stewart ,  John S. Dodson

IPC分类号： B24B9/16 ,  G01B11/02 ,  G01N21/87 ,  B28D5/00

CPC分类号： G01B11/022 ,  B24B9/162 ,  G01N21/87

摘要： A rough gem stone is centered by mounting the stone on a dop, providing an image of the stone, as seen normal to the axis, providing a reference shape which corresponds to the shape of a cut stone, and superimposing the stone image and the reference shape, altering the size of one relative to the other until the reference shape corresponds to the stone that can be cut from the rough stone, and altering the position of the rough stone until the stone image registers correctly with the reference shape. In a method of working the stone, the final radial dimension to which the stone is to be worked is estimated and is used for terminating working when the actual radial dimension reaches the corresponding value.

摘要翻译： 粗糙的宝石以将石头安装在多面体上为中心，提供与轴垂直的石头的图像，提供对应于切割石头的形状的参考形状，并且叠加石头图像和参考 形状，改变一个相对于另一个的尺寸，直到参考形状对应于可以从粗糙的石头切割的石头，并且改变粗糙石头的位置，直到石头图像正确地参考参考形状。 在工作石头的方法中，估计石头要被加工的最终径向尺寸，并且当实际径向尺寸达到相应值时用于终止工作。