公开(公告)号：US08285998B2

公开(公告)日：2012-10-09

申请号：US12442995

申请日：2007-09-28

申请人： Isao Echizen ,  Takaaki Yamada ,  Nobuharu Miura ,  Michiro Maeta ,  Takashi Mizuno

发明人： Isao Echizen ,  Takaaki Yamada ,  Nobuharu Miura ,  Michiro Maeta ,  Takashi Mizuno

IPC分类号： H04L9/32

CPC分类号： G06T1/0042 ,  G06T1/0085 ,  H04N21/44008 ,  H04N21/8352 ,  H04N21/8358

摘要： Regularity information such as time codes embedded preliminarily through an electronic watermark is detected from a predetermined number of pieces of continuous frame data of video content through the electronic watermark. In the case where the electronic watermark is not detected from the predetermined number of pieces of continuous frame data, a non-detection count is calculated, and falsification of the predetermined number of pieces of frame data is determined on the basis of the detected regularity information and the non-detection count. Accordingly, falsification such as deletion, addition, and replacement of video content is detected with high accuracy using the electronic watermark.

摘要翻译： 通过电子水印从预定数量的视频内容的连续帧数据中检测诸如通过电子水印预先嵌入的时间码的规律性信息。 在从预定数量的连续帧数据未检测到电子水印的情况下，计算非检测计数，并且基于检测到的规律性信息来确定预定数量的帧数据的伪造 和非检测计数。 因此，使用电子水印以高精度检测诸如删除，添加和替换视频内容的伪造。

公开(公告)号：US07675143B2

公开(公告)日：2010-03-09

申请号：US11976792

申请日：2007-10-29

申请人： Takahide Kadoyama ,  Masayoshi Abe ,  Atsushi Kamo ,  Takaaki Yamada ,  Chihiro Arai

发明人： Takahide Kadoyama ,  Masayoshi Abe ,  Atsushi Kamo ,  Takaaki Yamada ,  Chihiro Arai

IPC分类号： H01L23/552

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/642 ,  H01L23/66 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal ring and an external low-impedance node.

摘要翻译： 提供能够通过密封环减少传播到另一电路的电路的噪声的半导体元件。 半导体元件在半导体衬底的表面上包括多个电路; 围绕所述多个电路的环形密封环; 以及连接密封环和外部低阻抗节点之间的接线。

公开(公告)号：US20090249491A1

公开(公告)日：2009-10-01

申请号：US12342132

申请日：2008-12-23

申请人： Nobuharu Miura ,  Michiro Maeta ,  Takaaki Yamada ,  Yoshiyasu Takahashi

发明人： Nobuharu Miura ,  Michiro Maeta ,  Takaaki Yamada ,  Yoshiyasu Takahashi

IPC分类号： G06F21/00

CPC分类号： G06F21/10 ,  G06F2221/0737 ,  G06F2221/2101 ,  G06F2221/2151

摘要： The problem to be solved is to allow anyone other than the contents license owner to acquire a right usage opportunity of contents while the fraud in the contents can be detected. To solve this problem, a contents ID, distribution media information specifying the distribution media of the contents, and identification information containing distribution period information specifying the distribution period of the contents are attached to the contents body When a contents acceptance module 140 receives the contents data, an acquisition pattern recognition unit 142 recognizes the acquisition pattern information of the contents data. A identification information extraction module 154 of a contents validity determination module 150 extracts identification information from the contents data. A validity determination unit 153 compares the condition specified by this identification information with the contents acquisition media and the acquisition period indicated by the acquisition pattern information and if the acquisition pattern information satisfies the condition specified by the identification information, the contents data is stored in the contents-for-distribution file 126. Additionally, if the contents are determined to be illegal a deletion request is sent to the requestor.

摘要翻译： 要解决的问题是允许除内容许可证所有者以外的任何人获取内容的正确使用机会，同时可以检测到内容中的欺诈。 为了解决这个问题，内容ID，指定内容的分发媒体的分发媒体信息以及指定内容分发期间的分发期间信息的识别信息被附加到内容主体当内容接收模块140接收到内容数据 ，获取模式识别单元142识别内容数据的获取模式信息。 内容有效性确定模块150的识别信息提取模块154从内容数据中提取识别信息。 有效性确定单元153将由该识别信息指定的条件与由获取模式信息指示的内容获取介质和获取周期进行比较，并且如果获取模式信息满足由识别信息指定的条件，则将内容数据存储在 内容分发文件126.另外，如果内容被确定为非法，则将删除请求发送到请求者。

公开(公告)号：US07577843B2

公开(公告)日：2009-08-18

申请号：US10862875

申请日：2004-06-08

申请人： Isao Echizen ,  Takao Arai ,  Hiroyuki Kimura ,  Takaaki Yamada ,  Yasuhiro Fujii

发明人： Isao Echizen ,  Takao Arai ,  Hiroyuki Kimura ,  Takaaki Yamada ,  Yasuhiro Fujii

IPC分类号： H04N7/167 ,  G06K9/00

CPC分类号： G06T1/0071 ,  G06T2201/0064 ,  H04N5/913 ,  H04N21/4334 ,  H04N21/4627 ,  H04N21/8355 ,  H04N21/8358 ,  H04N2005/91328 ,  H04N2005/91335

摘要： At least one kind of control signal concerning control of contents, added to specific locations inside contents data, is detected as first control information, and at the same time, at least one kind of control information concerning control of contents, embedded inside the contents data by a digital watermark, is detected as second control information. Consistency between the first control information as detected, and the second control information as detected is determined and on the basis of results of the determination, the control of the contents is executed. Thus, it is possible to reduce a possibility of the contents being improperly copied, thereby enabling the control with assurance of still higher safety.

摘要翻译： 作为第一控制信息，检测到与内容数据内的特定位置相关的内容的控制中的至少一种控制信号，同时，嵌入在内容数据内的内容的控制的至少一种控制信息 被检测为第二控制信息。 确定检测到的第一控制信息和检测到的第二控制信息之间的一致性，并且基于确定的结果，执行内容的控制。 因此，可以降低内容物的不正确复制的可能性，从而能够进一步确保安全性的控制。

公开(公告)号：US07489507B2

公开(公告)日：2009-02-10

申请号：US10970290

申请日：2004-10-21

申请人： Toru Karashima ,  Takaaki Morimura ,  Takaaki Yamada

发明人： Toru Karashima ,  Takaaki Morimura ,  Takaaki Yamada

IPC分类号： H05K5/00 ,  H05K7/00 ,  A47B81/00 ,  E05D7/00

CPC分类号： G06F1/1616 ,  G06F1/1658 ,  G06F1/1681 ,  Y10T16/52

摘要： A power switch and connector that are conventionally included in a body are formed in spaces created at the outer ends of the shafts of hinges other than the body and a display, whereby the body is thinned. Electronic device comprises a body, a display, and a hinge that joins the body and display so that they can be freely opened or closed. A power switch is formed at an end of the shaft of the hinge. Furthermore, the electronic device comprises the body, the display, and another hinge that joins the body and display so that they can be freely opened or closed. A port of a connector opens at an end of the shaft of the hinge.

摘要翻译： 通常包括在主体中的电源开关和连接器形成在除了主体和显示器之外的铰链轴的外端处产生的空间中，由此主体变薄。 电子设备包括主体，显示器和连接主体和显示器的铰链，使得它们可以自由地打开或关闭。 电源开关形成在铰链的轴的端部。 此外，电子设备包括主体，显示器和连接主体和显示器的另一铰链，使得它们可以自由地打开或关闭。 连接器的端口在铰链的轴的端部处开口。

公开(公告)号：US06366909B1

公开(公告)日：2002-04-02

申请号：US09178540

申请日：1998-10-26

申请人： Toshiyuki Yuasa ,  Takaaki Yamada ,  Hiroyuki Kojima ,  Masato Tsuchibora

发明人： Toshiyuki Yuasa ,  Takaaki Yamada ,  Hiroyuki Kojima ,  Masato Tsuchibora

IPC分类号： G06F1730

CPC分类号： G06F17/3097 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935

摘要： An information presentation apparatus includes an information organization structure editing unit, a search condition creating unit, an information collection unit, and a collection result joining unit. The editing unit prompts a user to enter plural terms and one or more relations among said terms and store them as an information organization structure. The search condition creating unit creates a search condition of information from the terms and the relations among the terms stored in the information organization structure. The information collection unit searches information storage by using the created search condition and collect location information of the data meeting the search condition. The collection result joining unit visually joins the terms and the relations among the terms stored in the information organization structure with the location information of the searched data and displays the joined result.

摘要翻译： 信息呈现装置包括信息组织结构编辑单元，搜索条件创建单元，信息收集单元和收集结果加入单元。 编辑单元提示用户输入复数项和所述术语中的一个或多个关系，并将它们存储为信息组织结构。 搜索条件创建单元从存储在信息组织结构中的术语和术语之间的关系创建信息的搜索条件。 信息收集单元通过使用所创建的搜索条件来搜索信息存储，并且收集满足搜索条件的数据的位置信息。 收集结果加入单元将存储在信息组织结构中的项与术语之间的关系与搜索到的数据的位置信息进行视觉上的连接，并显示加入结果。

公开(公告)号：US5623224A

公开(公告)日：1997-04-22

申请号：US524118

申请日：1995-08-24

申请人： Takaaki Yamada ,  Yasushi Nakamoto

发明人： Takaaki Yamada ,  Yasushi Nakamoto

IPC分类号： G05F3/24 ,  G06K19/07 ,  G05F1/56

CPC分类号： G06K19/0701 ,  G05F3/247 ,  G06K19/0723

摘要： A communication circuit system of an IC card etc. including a voltage drop circuit having a complementary type transistor circuit comprising a p-channel and an n-channel transistor connected together, the circuit being connected to a power source voltage and generating a voltage corresponding to the sum of the threshold voltages of the p-channel transistor and n-channel transistor and supplying the same to a load circuit; an oscillation circuit having a complementary MOS inverter, a capacitor connected to the input side of the complementary MOS inverter, and resistance elements connected between the input and output of the complementary MOS inverter; and a wave detection circuit having a first and second MOS transistors with drains and gates connected to each other and a current source, nodes between the drains and the gates of the first and second MOS transistors being connected to the current source, the gate of the first MOS transistor being connected to a signal input line, and the current capacity of the second MOS transistor being set larger than the current capacity of the first MOS transistor.

摘要翻译： 一种IC卡等的通信电路系统，包括具有互连型晶体管电路的电压降电路，所述互补型晶体管电路包括连接在一起的p沟道和n沟道晶体管，所述电路连接到电源电压并产生对应于 p沟道晶体管和n沟道晶体管的阈值电压之和并将其提供给负载电路; 具有互补MOS反相器的振荡电路，连接到互补MOS反相器的输入侧的电容器和连接在互补MOS反相器的输入和输出之间的电阻元件; 以及波形检测电路，具有具有彼此连接的漏极和栅极的第一和第二MOS晶体管和电流源，第一和第二MOS晶体管的漏极和栅极之间的节点连接到电流源， 第一MOS晶体管连接到信号输入线，并且第二MOS晶体管的电流容量被设定为大于第一MOS晶体管的电流容量。

公开(公告)号：US5404168A

公开(公告)日：1995-04-04

申请号：US19872

申请日：1993-02-19

申请人： Takaaki Yamada ,  Naofumi Yanagihara ,  Hiroshi Okada

发明人： Takaaki Yamada ,  Naofumi Yanagihara ,  Hiroshi Okada

IPC分类号： H04N5/92 ,  H04N5/926 ,  H04N19/126 ,  H04N19/134 ,  H04N19/149 ,  H04N19/174 ,  H04N19/186 ,  H04N19/192 ,  H04N19/196 ,  H04N19/42 ,  H04N19/59 ,  H04N19/60 ,  H04N19/625 ,  H04N19/65 ,  H04N19/70 ,  H04N19/88 ,  H04N19/91 ,  H04N7/133

CPC分类号： H04N5/9264 ,  H04N19/126 ,  H04N19/149 ,  H04N19/15 ,  H04N19/176 ,  H04N19/60 ,  H04N19/85 ,  H04N19/88 ,  H04N19/13 ,  H04N19/146 ,  H04N19/91

摘要： A quantizing number is determined using multiple stages of code amount estimating circuits. Thus, an optimum quantizing number may be selected from among a number of quantizing numbers which is not limited to the number of code amount estimating circuits. The optimum quantizing number is used to quantize a set of blocks of orthogonally transformed image data. The quantized data are encoded using a variable length code. The optimum quantizing number is the one which results in the greatest amount of data that is within a predetermined threshold, permitting an amount of encoded data to be recorded on a magnetic tape in a fixed format.

摘要翻译： 使用多级代码量估计电路确定量化数。 因此，可以从不限于代码量估计电路的数量的多个量化数中选择最佳量化数。 最佳量化数用于量化一组正交变换图像数据块。 量化数据使用可变长度码进行编码。 最佳的量化数是导致最大数据量在预定阈值内的数量，允许以固定格式将一定数量的编码数据记录在磁带上。

公开(公告)号：US5023615A

公开(公告)日：1991-06-11

申请号：US482085

申请日：1990-02-20

申请人： Takaaki Yamada ,  Kazutoshi Shimizume

发明人： Takaaki Yamada ,  Kazutoshi Shimizume

IPC分类号： H01L27/092 ,  H03M1/82

CPC分类号： H01L27/092 ,  H01L2224/48091 ,  H01L2924/19107 ,  H03M1/822

摘要： In a digital-to-analog converter for converting a received digital signal having N bits and a sampling frequency fs to an analog signal; digital interpolation filter receives the digital signal and generates a modified digital signal having a number of bits less than N and a sampling frequency greater than fs, pulse width modulator receives the modified digital signal and generates a pulse signal having pulse widths which correspond to the modified digital signal, output buffer having a complementary metal oxide semiconductor (CMOS) inverter circuit including P channel and N channel transistors having respective resistance values receives the pulse signal and low-pass filter receives the output signal from the output buffer, wherein the digital interpolation filter, the pulse width modulator and the output buffer are formed in an integrated circuit, and when the transistors are conductive the resistance values of the P channel and N channel transistors are set equal to each other by adjusting a voltage applied to the integrated circuit substrate so as to improve the signal-to-noise ratio of the produced analog signal.

摘要翻译： 在用于将具有N位和采样频率fs的接收数字信号转换为模拟信号的数模转换器中， 数字内插滤波器接收数字信号并产生具有小于N的位数和大于fs的采样频率的修改数字信号，脉冲宽度调制器接收修改的数字信号，并产生具有对应于修改的数字信号的脉冲宽度的脉冲信号 数字信号，具有包括P沟道的互补金属氧化物半导体（CMOS）反相器电路和具有各自电阻值的N沟道晶体管的输出缓冲器接收脉冲信号，低通滤波器从输出缓冲器接收输出信号，其中数字插值滤波器 ，脉冲宽度调制器和输出缓冲器形成在集成电路中，并且当晶体管导通时，P沟道和N沟道晶体管的电阻值通过调整施加到集成电路衬底的电压而彼此相等， 以提高产生的模拟信号的信噪比。

公开(公告)号：US4533903A

公开(公告)日：1985-08-06

申请号：US396499

申请日：1982-07-08

申请人： Takaaki Yamada ,  Takeo Sekino

发明人： Takaaki Yamada ,  Takeo Sekino

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03K13/175

CPC分类号： H03M1/361

摘要： An analog-to-digital converter for converting an analog input voltage signal to a digital output voltage signal of m upper bits and n lower bits includes at least (2.sup.m+n -1) resistors connected in a series circuit to a voltage source for establishing respective reference voltages; at least (2.sup.m -1) upper bit voltage comparators for generating outputs indictive of the m upper bits, and having first and second inputs, the analog input voltage being applied to the first inputs and the second inputs being connected to the series circuit at respective intervals defining groups of the resistors; an upper bit encoder receiving the outputs of the upper bit voltage comparators and generating a switch control signal and a digital output voltage signal of m upper bits; at least (2.sup.n -1) lower bit voltage comparators for generating outputs indicative of the n lower bits, and having first and second inputs, the analog input voltage signal being applied also to the first inputs of the lower bit voltage comparators; switch elements associated with each of the groups and being responsive to the switch control signal for selectively connecting the second inputs of the lower bit comparators to respective resistors in the associated resistor groups; and a lower bit encoder receiving the outputs of the lower bit voltage comparators and generating a digital output voltage signal of n lower bits.

摘要翻译： 用于将模拟输入电压信号转换为m个高位和n个低位的数字输出电压信号的模数转换器包括连接到电压源的串联电路中的至少（2m + n-1）个电阻器，用于建立 各参考电压; 用于产生指示m个高位的输出的至少（2m-1）个高位电压比较器，并且具有第一和第二输入，模拟输入电压施加到第一输入端，第二输入端分别连接到串联电路 定义电阻组的间隔; 接收上位电压比较器的输出并产生开关控制信号和m位高位数字输出电压信号的高位编码器; 至少（2n-1）个低位电压比较器，用于产生指示n个较低位的输出，并且具有第一和第二输入，模拟输入电压信号也被施加到低位电压比较器的第一输入; 开关元件与每个组相关联并且响应于开关控制信号，用于选择性地将低位比较器的第二输入连接到相关电阻器组中的相应电阻器; 以及接收低位电压比较器的输出并产生n个较低位的数字输出电压信号的低位编码器。