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    CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT
    11.
    发明申请
    CONTROL DEVICE AND COMPUTER PROGRAM PRODUCT 审中-公开
    控制设备和计算机程序产品

    公开(公告)号：US20130091372A1

    公开(公告)日：2013-04-11

    申请号：US13622514

    申请日：2012-09-19

    申请人： Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Masaya Tarui ,  Satoshi Shirai ,  Akihiro Shibata

    发明人： Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Masaya Tarui ,  Satoshi Shirai ,  Akihiro Shibata

    IPC分类号： G06F1/30

    CPC分类号： G06F1/32 ,  G06F1/26

    摘要： According to an embodiment, a control device includes a receiving unit, a judging unit, an estimating unit, a deciding unit, a directing unit, and a sending unit. The receiving unit is configured to receive an interrupt request requesting a processing device that includes elements capable of being individually subjected to voltage control to execute an interrupt process. The judging unit is configured to judge a state of the elements. The estimating unit is configured to estimate a start-up time for the element to change into an operating mode after power is supplied. The deciding unit is configured to decide a starting point in time at which power supply is to be started on basis of a difference in the start-up times between the elements. The directing unit is configured to direct a power supply unit for supplying power to the elements. The sending unit is configured to send the interrupt request.

    摘要翻译： 根据实施例，控制装置包括接收单元，判断单元，估计单元，判定单元，引导单元和发送单元。 接收单元被配置为接收请求处理设备的中断请求，该处理设备包括能够单独经受电压控制的元件以执行中断处理。 判断单元被配置为判断元件的状态。 估计单元被配置为在供电之后估计元件变为操作模式的启动时间。 决定单元被配置为基于元件之间的启动时间的差异来确定要开始电源的时间点的起始点。 引导单元被配置为引导供电单元向元件供电。 发送单元配置为发送中断请求。

    CACHE MEMORY DEVICE, PROCESSOR, AND INFORMATION PROCESSING APPARATUS
    14.
    发明申请
    CACHE MEMORY DEVICE, PROCESSOR, AND INFORMATION PROCESSING APPARATUS 审中-公开
    高速缓存存储器，处理器和信息处理设备

    公开(公告)号：US20130073812A1

    公开(公告)日：2013-03-21

    申请号：US13546274

    申请日：2012-07-11

    申请人： Tatsunori Kanai ,  Tetsuro Kimura ,  Koichi Fujisaki ,  Haruhiko Toyama

    发明人： Tatsunori Kanai ,  Tetsuro Kimura ,  Koichi Fujisaki ,  Haruhiko Toyama

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

    摘要： According to an embodiment, a cache memory device caches data stored in or data to be stored in a memory device. The cache memory device includes a memory area that includes a plurality of cache lines; and a controller. When the number of dirty lines among the cache lines exceeds a predetermined number, the controller writes data of the dirty lines into the memory device, each of the dirty lines containing data that is not written in the memory device.

    摘要翻译： 根据实施例，高速缓冲存储器设备缓存存储在存储设备中的数据或数据。 高速缓冲存储器装置包括：包括多个高速缓存线的存储区; 和控制器。 当高速缓存线中的脏线数量超过预定数量时，控制器将脏线的数据写入存储器件，每条脏线包含未写入存储器件的数据。

    Memory system having an encoding processing circuit for redundant encoding process
    18.
    发明授权
    Memory system having an encoding processing circuit for redundant encoding process 有权
    具有用于冗余编码处理的编码处理电路的存储器系统

    公开(公告)号：US09105358B2

    公开(公告)日：2015-08-11

    申请号：US13157396

    申请日：2011-06-10

    申请人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada

    发明人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada

    IPC分类号： G06F11/16 ,  G06F11/10 ,  G11C29/04 ,  G11C29/42 ,  G06F11/08 ,  H03M13/19

    CPC分类号： G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/08 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1666 ,  G11C29/42 ,  H03M13/19

    摘要： In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.

    摘要翻译： 在一个实施例中，用于写入由编码处理电路输出的冗余数据的存储器系统包括存储器，编码处理电路和解码电路。 存储器通过使用存储器单元进行电可重写。 存储单元能够分别具有对应于逻辑值1或0的两个不同的电阻值。 读取冗余数据，并且通过沿相同方向流动电流将预定的逻辑值写入存储器。 编码处理电路对目标数据进行冗余编码处理，并输出冗余数据。 具有预定逻辑值的位数超过具有除了预定逻辑值之外的逻辑值的比特数，用于将冗余数据写入存储器。 解码电路从存储器读取数据，并对数据进行解码处理。

    Memory device
    19.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09075742B2

    公开(公告)日：2015-07-07

    申请号：US13360989

    申请日：2012-01-30

    申请人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    发明人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C29/04

    CPC分类号： G06F11/1048 ,  G11C2029/0411

    摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

    摘要翻译： 根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位， 以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相 所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

    MEMORY DEVICE
    20.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20120131418A1

    公开(公告)日：2012-05-24

    申请号：US13360989

    申请日：2012-01-30

    申请人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    发明人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    IPC分类号： G11C29/52 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  G11C2029/0411

    摘要： According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

    摘要翻译： 根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位， 以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相 所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。