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11.发明授权公开(公告)号：US06671644B2
公开(公告)日：2003-12-30
申请号：US09930355
申请日：2001-08-15
IPC分类号： G06F1100
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.
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公开(公告)号：US06170078A
公开(公告)日：2001-01-02
申请号：US09032567
申请日：1998-02-27
IPC分类号： G06F1750
CPC分类号： G01R31/318342
摘要： A system and method for the fault simulation testing of circuits by using a behavioral model is provided. The behavioral model includes a fault bus, decoder, and input and output ports. The decoder decodes mapping fault values, which are applied to the fault bus, to either a no-fault or to a specific fault which is internally encoded into the behavioral model. Accordingly, a single behavioral model can be used to dynamically model a fault-free circuit or machine and one or more faulty circuits or machines based on the mapping fault data applied to each model's fault bus. A fault simulation tool applies test simulation data having mapping fault and test parameter data to at least two identically coded behavioral models (i.e., a fault-free model and a faulty model, as defined by the applied mapping fault data). Output data are generated by each behavioral model and recorded by the fault simulation tool. A comparison of the output data of the fault-free behavioral model and the at least one faulty behavioral model is performed to determine whether the test pattern data detected differences therebetween.
摘要翻译： 提供了一种通过使用行为模型对电路进行故障模拟测试的系统和方法。 行为模型包括故障总线，解码器和输入和输出端口。 解码器将应用于故障总线的故障值映射到内部编码到行为模型中的无故障或特定故障。 因此，可以使用单个行为模型来基于应用于每个模型的故障总线的映射故障数据来动态地建模无故障电路或机器以及一个或多个故障电路或机器。 故障仿真工具将具有映射故障和测试参数数据的测试仿真数据应用于至少两个相同编码的行为模型（即，由应用的映射故障数据定义的无故障模型和故障模型）。 输出数据由每个行为模型生成并由故障模拟工具记录。 执行无故障行为模型的输出数据与至少一个故障行为模型的比较，以确定测试模式数据是否检测到差异。
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公开(公告)号：US07895487B2
公开(公告)日：2011-02-22
申请号：US11687003
申请日：2007-03-16
CPC分类号： G01R31/318566 , G11B20/1816
摘要： A structure and method for optimzing scan chain fail disgnosis. First, logic paths from target latches in a target scan chain to observation latches in at least one other observation scan chain are identified. Then, the locations of the observation latches within the other scan chains are optimized.
摘要翻译： 用于优化扫描链失败的结构和方法失败。 首先，识别从目标扫描链中的目标锁存器到至少一个其它观察扫描链中的观察锁存器的逻辑路径。 然后，优化了其他扫描链内观测锁存器的位置。
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公开(公告)号：US07240261B2
公开(公告)日：2007-07-03
申请号：US10707373
申请日：2003-12-09
CPC分类号： G01R31/318566 , G11B20/1816
摘要： A structure and method for performing scan chain diagnosis. The structure comprises a diagnosed/target scan chain and one or more good observation scan chains. Observing logic paths from the target scan chain to observation scan chains can be identified according to a pre-specified criterion. The diagnosed scan chain is loaded in series with a test pattern. Then, the contents of the observed latch(es) in the diagnosed scan chain propagate through the observing logic paths. Then, the output signals of the observing logic paths are strobed into the observing latch(es) in the observing scan chain(s). Then, the observing scan chain(s) are unloaded and the contents of the observing latch(es) are collected and analyzed to determine the defect types and the defect ranges in the diagnosed scan chain.
摘要翻译： 用于执行扫描链诊断的结构和方法。 该结构包括诊断/目标扫描链和一个或多个良好的观察扫描链。 可以根据预先指定的标准来识别从目标扫描链到观察扫描链的逻辑路径。 诊断的扫描链与测试图案串联加载。 然后，诊断的扫描链中观察到的锁存器的内容通过观察逻辑路径传播。 然后，观测逻辑路径的输出信号被选通到观测扫描链中的观测锁存器中。 然后，观察扫描链被卸载，并且收集和分析观察锁存器的内容以确定诊断的扫描链中的缺陷类型和缺陷范围。
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公开(公告)号：US06954916B2
公开(公告)日：2005-10-11
申请号：US10604179
申请日：2003-06-30
CPC分类号： G06F17/5022
摘要： A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.
摘要翻译： 一种用于模拟集成电路的方法和系统。 该方法包括以下步骤：执行电路的定时分析，以确保它们满足规定的时序准则，执行电路的软错误分析，以确定它们是否符合指定的软错误标准，以及改进那些无法通过软错误分析的电路 提高其对软错误的抵抗力，并且在时序上没有劣化。 优选地，改进步骤包括通过具有附加电压源或改变电路的电容来改进不能通过软误差分析的那些电路的步骤。
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16.发明授权公开(公告)号：US06865501B2
公开(公告)日：2005-03-08
申请号：US10697365
申请日：2003-10-30
IPC分类号： G01R31/319 , G01R31/3193 , G06F19/00
CPC分类号： G01R31/31725 , G01R31/318594 , G01R31/31922 , G01R31/31937
摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.
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公开(公告)号：US06721914B2
公开(公告)日：2004-04-13
申请号：US09827425
申请日：2001-04-06
IPC分类号： G01R3128
CPC分类号： G01R31/317
摘要： A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.
摘要翻译： 一种用于诊断集成电路中的缺陷的方法，包括：提供一组故障测试图案; 对于测试模式集合中的每个故障测试模式，确定单个卡住故障是否可能导致故障测试模式，并确定导致单个卡住故障的故障可能存在的节点; 选择可能由单一故障引起的故障测试模式; 并且对于那些选择的故障测试模式来确定第一组节点，使得所选择的故障测试模式中的每一个可能由每个节点上的至少一个节点上的卡住零或卡住的一个导致 从第一组节点。
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公开(公告)号：US07313744B2
公开(公告)日：2007-12-25
申请号：US10708380
申请日：2004-02-27
IPC分类号： G01R31/28
CPC分类号： G01R31/318533
摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.
摘要翻译： 提供了用于隔离扫描链中的缺陷的系统，方法和装置。 本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。 扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值， 到了错误。 这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。 提供了许多其他方面。
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公开(公告)号：US06901542B2
公开(公告)日：2005-05-31
申请号：US09927011
申请日：2001-08-09
申请人： Thomas W. Bartenstein , L. Owen Farnsworth, III , Douglas C. Heaberlin , Edward E. Horton, III , Leendert M. Huisman , Leah M. Pastel , Glen E. Richard , Raymond J. Rosner , Francis Woytowich
发明人： Thomas W. Bartenstein , L. Owen Farnsworth, III , Douglas C. Heaberlin , Edward E. Horton, III , Leendert M. Huisman , Leah M. Pastel , Glen E. Richard , Raymond J. Rosner , Francis Woytowich
IPC分类号： G11C29/26 , G01R31/3193 , G01R31/3177 , G01R31/3187
CPC分类号： G11C29/26
摘要： A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.
摘要翻译： 公开了一种测试具有存储器的半导体器件的方法。 该方法包括选择存储器的一部分; 测试存储器的选定部分; 响应于可接受的测试结果，将存储器的所选部分指定为指定存储器; 并在稍后的时间将数据存储在存储器的指定部分中以进行检索。 对所选择的存储器进行软修复。 测试数据可以在存储在指定的存储器中之前进行压缩。
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公开(公告)号：US06880136B2
公开(公告)日：2005-04-12
申请号：US10191212
申请日：2002-07-09
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Defects in manufacturing of IC devices are analyzed by testing the devices for defects using results of LSSD technology to find at least one failing pattern that contains incorrect values. The failing latches are used as a starting point to trace back through combinational logic feeding the failing latches, until controllable latches are encountered. A decision is then made to continue the back tracing or not depending on whether the latter latches were clocked during the application of one of the failing patterns or not.
摘要翻译： 通过使用LSSD技术的结果测试设备的缺陷来分析IC器件制造中的缺陷，以找到至少一个包含不正确值的故障模式。 使用故障锁存器作为起始点，通过组合逻辑来跟踪故障锁存器，直到遇到可控制的锁存器。 然后，决定是否在应用其中一种失败模式的情况下是否继续后跟踪。
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