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    UNIFORM LOAD PROCESSING FOR PARALLEL THREAD SUB-SETS
    12.
    发明申请
    UNIFORM LOAD PROCESSING FOR PARALLEL THREAD SUB-SETS 有权
    用于并联螺纹子组的均匀加载处理

    公开(公告)号：US20130232322A1

    公开(公告)日：2013-09-05

    申请号：US13412438

    申请日：2012-03-05

    申请人： Michael FETTERMAN ,  Stewart Glenn Carlton ,  Douglas J. Hahn ,  Rajeshwaran Selvanesan ,  Shirish Gadre ,  Steven James Heinrich

    发明人： Michael FETTERMAN ,  Stewart Glenn Carlton ,  Douglas J. Hahn ,  Rajeshwaran Selvanesan ,  Shirish Gadre ,  Steven James Heinrich

    IPC分类号： G06F9/312 ,  G06F9/38

    CPC分类号： G06F9/3887 ,  G06F9/383 ,  G06F9/3851

    摘要： One embodiment of the present invention sets forth a technique for processing load instructions for parallel threads of a thread group when a sub-set of the parallel threads request the same memory address. The load/store unit determines if the memory addresses for each sub-set of parallel threads match based on one or more uniform patterns. When a match is achieved for at least one of the uniform patterns, the load/store unit transmits a read request to retrieve data for the sub-set of parallel threads. The number of read requests transmitted is reduced compared with performing a separate read request for each thread in the sub-set. A variety of uniform patterns may be defined based on common access patterns present in program instructions. A variety of uniform patterns may also be defined based on interconnect constraints between the load/store unit and the memory when a full crossbar interconnect is not available.

    摘要翻译： 本发明的一个实施例提出了一种当并行线程的子集请求相同存储器地址时处理线程组的并行线程的加载指令的技术。 加载/存储单元确定每个并行线程子集的存储器地址是否基于一个或多个均匀模式相匹配。 当对至少一个均匀模式实现匹配时，加载/存储单元发送读取请求以检索用于并行线程子集的数据。 与对子集中的每个线程执行单独的读取请求相比，发送的读取请求的数量减少。 可以基于程序指令中存在的公共访问模式来定义各种均匀模式。 当完整的交叉互连不可用时，也可以基于加载/存储单元和存储器之间的互连约束来定义各种均匀模式。

    N-way memory barrier operation coalescing
    13.
    发明授权
    N-way memory barrier operation coalescing 有权
    N路记忆障碍操作合并

    公开(公告)号：US08997103B2

    公开(公告)日：2015-03-31

    申请号：US13441785

    申请日：2012-04-06

    申请人： Shirish Gadre ,  Charles McCarver ,  Anjana Rajendran ,  Omkar Paranjape ,  Steven James Heinrich

    发明人： Shirish Gadre ,  Charles McCarver ,  Anjana Rajendran ,  Omkar Paranjape ,  Steven James Heinrich

    IPC分类号： G06F9/46 ,  G06F1/04 ,  G06F7/00 ,  G06F9/38 ,  G06F9/30 ,  G06F9/52

    CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/522

    摘要： One embodiment sets forth a technique for N-way memory barrier operation coalescing. When a first memory barrier is received for a first thread group execution of subsequent memory operations for the first thread group are suspended until the first memory barrier is executed. Subsequent memory barriers for different thread groups may be coalesced with the first memory barrier to produce a coalesced memory barrier that represents memory barrier operations for multiple thread groups. When the coalesced memory barrier is being processed, execution of subsequent memory operations for the different thread groups is also suspended. However, memory operations for other thread groups that are not affected by the coalesced memory barrier may be executed.

    摘要翻译： 一个实施例提出了一种用于N路存储器屏障操作合并的技术。 当为第一线程组接收到第一存储器障碍时，对于第一线程组的后续存储器操作的执行被暂停，直到执行第一存储器障碍。 不同线程组的后续内存障碍可以与第一存储器屏障合并，以产生代表多个线程组的存储器屏障操作的聚结存储器屏障。 当合并的存储器障碍被处理时，对于不同的线程组的后续存储器操作的执行也被暂停。 然而，可以执行不受聚结的存储器屏障影响的其他线程组的存储器操作。

    Memory controller providing dynamic arbitration of memory commands
    18.
    发明授权
    Memory controller providing dynamic arbitration of memory commands 失效
    存储器控制器提供存储器命令的动态仲裁

    公开(公告)号：US06922770B2

    公开(公告)日：2005-07-26

    申请号：US10446333

    申请日：2003-05-27

    申请人： Venkatachalam Shanmugasundaram ,  Edward Paluch ,  Shirish Gadre ,  Jean Kao

    发明人： Venkatachalam Shanmugasundaram ,  Edward Paluch ,  Shirish Gadre ,  Jean Kao

    IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F13/16

    CPC分类号： G06F13/1621 ,  G06F2213/0038

    摘要： Embodiments of the present invention provide a memory controller comprising a front-end module, a back-end module communicatively coupled to the front-end module, and a physical interface module communicatively coupled to the back-end module. The front-end module generates a plurality of page packets from a plurality of received memory commands, wherein the order of receipt of said memory commands is preserved. The back-end module dynamically issues a next one of the plurality of page packets while issuing a current one of the plurality of page packets. The physical interface module causes a plurality of transfers according to the dynamically issued current one and next one of the plurality of page packets.

    摘要翻译： 本发明的实施例提供了一种存储器控制器，其包括前端模块，通信地耦合到前端模块的后端模块以及通信地耦合到后端模块的物理接口模块。 前端模块从多个接收到的存储器命令生成多个页面包，其中保存所述存储器命令的接收顺序。 后端模块在发布多个页面分组中的当前页面分组的同时动态地发出多个页面分组中的下一个分组。 物理接口模块根据多个页面分组中的动态发布的当前一个和下一个页面进行多个传输。

    Method and apparatus for efficiently allocating memory in audio still video (ASV) applications
    20.
    发明授权
    Method and apparatus for efficiently allocating memory in audio still video (ASV) applications 失效
    用于在音频静止视频（ASV）应用中有效分配存储器的方法和装置

    公开(公告)号：US07167640B2

    公开(公告)日：2007-01-23

    申请号：US10074390

    申请日：2002-02-11

    申请人： Shirish Gadre ,  Fang-Chuan Wu ,  Elif Albuz ,  Raman Subramanian

    发明人： Shirish Gadre ,  Fang-Chuan Wu ,  Elif Albuz ,  Raman Subramanian

    IPC分类号： H04N5/00 ,  H04N5/91

    CPC分类号： H04N9/8042 ,  G11B20/10 ,  G11B2020/10675 ,  H04N5/85 ,  H04N9/8063 ,  H04N9/8205 ,  H04N9/8211 ,  H04N9/8227 ,  H04N21/42646 ,  H04N21/44004 ,  H04N21/8153

    摘要： A dynamic allocation of available ASV buffer memory space is performed on each pack in a DVD-A bitstream one pack at a time. Concurrently, an ASV buffer table is updated for each type of data pack currently being processed. The ASV buffer table includes pointers corresponding to the various fields that form a particular ASV frame. In this way, only that memory that is required to store a particular ASV frame is used thereby allowing the ASV buffer memory to be configured on the fly in such a manner as to efficiently store the required ASV frame data. When a particular ASV frame is to be displayed, or otherwise processed, the ASV buffer table is accessed, and the particular pointers for a specific ASV frame are looked up and used to access the desired ASV frame.

    摘要翻译： 在DVD-A比特流中一次一包地对每个包上的可用ASV缓冲存储器空间进行动态分配。 同时，针对当前正在处理的每种类型的数据包更新ASV缓冲表。 ASV缓冲表包括与形成特定ASV帧的各种字段对应的指针。 以这种方式，仅使用存储特定ASV帧所需的存储器，从而允许在运行中配置ASV缓冲存储器，以便有效地存储所需的ASV帧数据。 当要显示或以其他方式处理特定ASV帧时，访问ASV缓冲表，并且查找特定ASV帧的特定指针以用于访问所需的ASV帧。