公开(公告)号：US07287103B2

公开(公告)日：2007-10-23

申请号：US11130911

申请日：2005-05-17

申请人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Charles Ray Johns ,  Peichun Peter Liu

发明人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Charles Ray Johns ,  Peichun Peter Liu

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G11C7/1006

摘要： A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

摘要翻译： 提供了一种方法，装置和计算机程序产品，用于处理XDR（TM）DRAM存储器系统中的写掩码操作。 本发明消除了对双端口阵列的需要，因为在接收到数据时完成了掩码生成。 掩码计算需要较少的逻辑，因为256个可能的字节值中只有144个被解码。 掩码值生成并存储在掩码数组中。 独立地，写入数据被存储在写入缓冲器中。 掩码值用于生成写掩码命令。 一旦写掩码命令被发出，写入数据和掩码值被发送到多路复用器。 多路器使用掩码值对写入数据进行掩码，以便将掩蔽的数据存储在XDR DRAMS中。

公开(公告)号：US08483227B2

公开(公告)日：2013-07-09

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/56

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US20090077322A1

公开(公告)日：2009-03-19

申请号：US11857674

申请日：2007-09-19

申请人： Charles Ray Johns ,  Roy Moonseuk Kim ,  Peichun Peter Liu ,  Shigehiro Asano ,  Anushkumar Rengarajan

发明人： Charles Ray Johns ,  Roy Moonseuk Kim ,  Peichun Peter Liu ,  Shigehiro Asano ,  Anushkumar Rengarajan

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/1016

摘要： A system and method for using a data-only transfer protocol to store atomic cache line data in a local storage area is presented. A processing engine includes an atomic cache and a local storage. When the processing engine encounters a request to transfer cache line data from the atomic cache to the local storage (e.g., GETTLAR command), the processing engine utilizes a data-only transfer protocol to pass cache line data through the external bus node and back to the processing engine. The data-only transfer protocol comprises a data phase and does not include a prior command phase or snoop phase due to the fact that the processing engine communicates to the bus node instead of an entire computer system when the processing engine sends a data request to transfer data to itself.

摘要翻译： 提出了一种使用仅数据传输协议将原始高速缓存行数据存储在本地存储区域中的系统和方法。 处理引擎包括原子缓存和本地存储。 当处理引擎遇到将高速缓存行数据从原子缓存传送到本地存储器（例如，GETTLAR命令）的请求时，处理引擎利用仅数据传输协议通过外部总线节点传递高速缓存行数据并返回 处理引擎。 仅数据传输协议包括数据相位，并且不包括先前的命令阶段或窥探阶段，因为当处理引擎发送数据请求传送时处理引擎与总线节点而不是整个计算机系统通信 数据本身。

公开(公告)号：US08611368B2

公开(公告)日：2013-12-17

申请号：US13162917

申请日：2011-06-17

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/43 ,  H04L12/28

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

公开(公告)号：US07187614B2

公开(公告)日：2007-03-06

申请号：US10965626

申请日：2004-10-14

申请人： Scott Raymond Cottier ,  Peichun Peter Liu ,  Shohji Onishi

发明人： Scott Raymond Cottier ,  Peichun Peter Liu ,  Shohji Onishi

IPC分类号： G11C8/00

CPC分类号： G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/413

摘要： An apparatus, a method, and a computer program product are provided for time reduction for an array read access control consisting of a bitcell with logic gating and a pull down device included, therein. To reduce gate delay this design implements gating logic inside the bitcell. The multiplex select gating signals are brought into the bitcell, and are gated with the data array. The gating logic controls the pull down device, and MUX select signals can be produced as a readout of the bitcell. This design reduces gate delay because the dependency upon the gating logic is overridden and the number of stages is reduced.

摘要翻译： 提供了一种装置，方法和计算机程序产品，用于对包括逻辑门控的位单元和包括其中的下拉装置的阵列读取访问控制进行时间缩减。 为了减少门延迟，该设计在位单元内部实现门控逻辑。 多路选择门控信号被带入位单元，并且被数据阵列选通。 门控逻辑控制下拉装置，并且可以产生MUX选择信号作为比特单元的读出。 该设计减少了门延迟，因为对门控逻辑的依赖性被覆盖，并且级数减少。

公开(公告)号：US07069390B2

公开(公告)日：2006-06-27

申请号：US10655401

申请日：2003-09-04

申请人： Wen-Tzer Thomas Chen ,  Peichun Peter Liu ,  Kevin C. Stelzer

发明人： Wen-Tzer Thomas Chen ,  Peichun Peter Liu ,  Kevin C. Stelzer

IPC分类号： G06F12/12

CPC分类号： G06F12/123 ,  G06F12/0802 ,  Y10S707/99945 ,  Y10S707/99948

摘要： The present invention provides for a plurality of partitioned ways of an associative cache. A pseudo-least recently used binary tree is provided, as is a way partition binary tree, and signals are derived from the way partition binary tree as a function of a mapped partition. Signals from the way partition binary tree and the pseudo-least recently used binary tree are combined. A cache line replacement signal is employable to select one way of a partition as a function of the pseudo-least recently used binary tree and the signals derived from the way partition binary tree.

摘要翻译： 本发明提供了关联高速缓存的多个分割方式。 提供了一种伪最近最少使用的二叉树，也是分配二叉树的一种方式，并且信号是从分配二叉树的方式导出的，作为映射分区的函数。 从分区二叉树和伪最小最近使用的二进制树的方式组合信号。 高速缓存行替换信号可用于根据伪最近最少使用的二叉树和从分区二叉树方式导出的信号来选择分区的一种方式。

公开(公告)号：US06983387B2

公开(公告)日：2006-01-03

申请号：US10273617

申请日：2002-10-17

申请人： David William Boerstler ,  Sang Hoo Dhong ,  Harm Peter Hofstee ,  Peichun Peter Liu

发明人： David William Boerstler ,  Sang Hoo Dhong ,  Harm Peter Hofstee ,  Peichun Peter Liu

IPC分类号： H03L7/06

CPC分类号： G06F1/06 ,  G06F1/10

摘要： Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.

摘要翻译： 公开了一种电子芯片，其包含分布在芯片的区域上的多个电子电路分区，每个电子部件分别包括处理器核心和与芯片的其他分区中的核心不同的时钟相位域。 相同频率的源，但是表示不同时钟域的不同相位时钟信号，为了减小瞬时幅度切换电流，向相邻分区提供不同的相位信号。 片内通信电路在分区之间分配控制和数据信号。

公开(公告)号：US06510493B1

公开(公告)日：2003-01-21

申请号：US09354127

申请日：1999-07-15

申请人： Peichun Peter Liu ,  Francis Patrick O'Connell

发明人： Peichun Peter Liu ,  Francis Patrick O'Connell

IPC分类号： G06F1200

CPC分类号： G06F12/128 ,  G06F12/0897

摘要： A cache memory having a mechanism for managing cache lines replacement is disclosed. The cache memory comprises multiple cache lines partitioned into a first group and a second group. The number of cache lines in the second group is preferably larger than the number of cache lines in the first group. A replacement logic block selectively chooses a cache line from one of the two groups of cache lines for replacement during an allocation cycle.

摘要翻译： 公开了一种具有用于管理高速缓存行替换的机制的高速缓冲存储器。 高速缓冲存储器包括分割成第一组和第二组的多个高速缓存行。 第二组中的高速缓存行的数量优选地大于第一组中的高速缓存行的数量。 替换逻辑块在分配周期期间有选择地从两组高速缓存线之一中选择一条高速缓存行进行替换。

公开(公告)号：US5890221A

公开(公告)日：1999-03-30

申请号：US319201

申请日：1994-10-05

申请人： Peichun Peter Liu ,  Brian David Branson

发明人： Peichun Peter Liu ,  Brian David Branson

IPC分类号： G06F12/10 ,  G06F12/08

CPC分类号： G06F12/1045

摘要： An interleaved data cache array which is divided into two sub arrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a first content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addresssable fields for the effective address and real address offset and alias problems may be efficiently resolved. A virtual address aliasing condition is identified by searching each cache line for a match between a portion of a desired effective address and the content of the first content addressable field. The desired effective address is translated into a desired real address and a portion of the desired real address is then utilized to search each cache line for a match with the content of the second content addressable field if no match was found within the first content addressable field during the previous cycle. An offset condition is identified by comparing the translated real address to the content of the second content addressable field in a cache line when a match has occurred between the desired effective address and the content of the first content addressable field within that cache line.

摘要翻译： 提供分割成两个子阵列的交错数据高速缓存阵列用于数据处理系统内的利用。 每个子阵列包括多条高速缓存线，其中每条高速缓存线包括所选择的数据块，奇偶校验字段，包含所选择的数据块的有效地址的一部分的第一内容可寻址字段，第二内容可寻址字段包含部分 的所选数据块的真实地址和数据状态字段。 通过利用两个单独的内容可寻址字段来实现有效地址和实际地址偏移，并且可以有效地解决别名问题。 通过搜索每个高速缓存行来确定虚拟地址混叠条件，以获得期望的有效地址的一部分与第一内容可寻址字段的内容之间的匹配。 将期望的有效地址转换成所需的实际地址，然后如果在第一内容可寻址字段内没有找到匹配，则利用所需实际地址的一部分来搜索每个高速缓存线与第二内容可寻址字段的内容的匹配 在上一个周期。 当在期望的有效地址与该高速缓存行内的第一内容可寻址字段的内容之间发生匹配时，通过比较翻译的实际地址与高速缓存行中的第二内容可寻址字段的内容来识别偏移条件。

公开(公告)号：US07107376B2

公开(公告)日：2006-09-12

申请号：US10764626

申请日：2004-01-26

申请人： Shigehiro Asano ,  Peichun Peter Liu ,  David Mui

发明人： Shigehiro Asano ,  Peichun Peter Liu ,  David Mui

IPC分类号： G06F13/362 ,  G06F13/372

CPC分类号： G06F13/3625

摘要： Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.

摘要翻译： 用于控制一组代理对资源的访问的系统和方法，其中代理具有与其相关联的相应优先级，以及与资源控制相关联的监视器，以及由代理基于优先级访问资源的位置。 一个实施例在具有连接到处理器总线的多个处理器的计算机系统中实现。 处理器总线包括整形监视器，其被配置为控制处理器对总线的访问。 整形监视器根据分配给处理器的优先级，尝试在整个基期内分配来自每个处理器的访问。 整形监视器根据其相对优先级向处理器分配插槽。 首先根据处理器的各自的带宽需求分配优先级，但是可以基于对总线的实际访问和期望访问的比较来修改优先级。