公开(公告)号：US20090256202A1

公开(公告)日：2009-10-15

申请号：US12102032

申请日：2008-04-14

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Souvick Mitra

IPC分类号： H01L29/786

CPC分类号： H01L27/1203 ,  H01L27/0248

摘要： Semiconductor-on-insulator device structures with enhanced electrostatic discharge protection, and design structures for an integrated circuit with device structures exhibiting enhanced electrostatic discharge protection. A device is formed in a body region of a device layer of a semiconductor-on-insulator substrate, which is bounded by an inner peripheral sidewall of an annular dielectric-filled isolation structure that extends from a top surface of the device layer to the insulating layer of the semiconductor-on-insulator substrate. An annular conductive interconnect extends through the body region and the insulating layer to connect the body region with the bulk wafer of the semiconductor-on-insulator substrate. The annular conductive interconnect is disposed inside the inner peripheral sidewall of the isolation structure, which annularly encircles the body region.

摘要翻译： 具有增强的静电放电保护的绝缘体上半导体器件结构以及具有增强的静电放电保护的器件结构的集成电路的设计结构。 一种器件形成在绝缘体上半导体衬底的器件层的体区中，该衬底由环形电介质填充的隔离结构的内周侧壁限定，该隔离结构从器件层的顶表面延伸到绝缘体 绝缘体上半导体衬底的层。 环形导电互连延伸穿过主体区域和绝缘层，以将体区域与绝缘体上半导体衬底的体晶片连接。 环形导电互连件设置在隔离结构的内周侧壁的内侧，环形环绕主体区域。

公开(公告)号：US20090160013A1

公开(公告)日：2009-06-25

申请号：US11960030

申请日：2007-12-19

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L29/00 ,  H01L21/4763

CPC分类号： H01L23/34 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/0255 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

摘要翻译： 半导体器件的发热元件位于半导体衬底中的两个重掺杂半导体区之间。 发热部件可以是具有轻掺杂的二极管的中间部分，可控硅整流器的阴极和阳极之间的轻掺杂p-n结或掺杂半导体电阻器的电阻部分。 至少一个包含金属或非金属导电材料的导热通孔直接放置在发热部件上。 或者，可以在发热部件和至少一个导热通孔之间形成薄介电层。 至少一个导热通孔可以连接到或可以不连接到后端金属线，其可以通过掩埋绝缘体层连接到较高级别的金属布线或者与手柄基板连接。

公开(公告)号：US08669146B2

公开(公告)日：2014-03-11

申请号：US13005560

申请日：2011-01-13

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L21/336

CPC分类号： H01L29/0688 ,  H01L27/0266 ,  H01L29/0615 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

摘要： A method of forming a semiconductor structure, including forming a channel in a first portion of a semiconductor layer and forming a doped extension region in a second portion of the semiconductor layer abutting the channel on a first side and abutting an insulator material on a bottom side. The first portion of the semiconductor layer is thicker than the second portion of the semiconductor layer.

公开(公告)号：US20120153434A1

公开(公告)日：2012-06-21

申请号：US12969004

申请日：2010-12-15

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/82 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

摘要翻译： 金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。 布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。

公开(公告)号：US07881028B2

公开(公告)日：2011-02-01

申请号：US12041962

申请日：2008-03-04

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H02H9/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device and/or circuit having an e-fuse is provided to disable a triggering network, and more specifically, an e-fuse is used to disable an electrostatic discharge (ESD) RC triggering network after device installation. The device and/or circuit includes a triggering network electrically coupled to an electrostatic discharge (ESD) protection device. An e-fuse is electrically coupled with the triggering network and configured to render the ESD protection device insensitive to a triggering signal after blowing the e-fuse.

摘要翻译： 提供具有电子保险丝的装置和/或电路以禁用触发网络，更具体地，使用电子熔丝来在设备安装之后禁用静电放电（ESD）RC触发网络。 该装置和/或电路包括电耦合到静电放电（ESD）保护装置的触发网络。 电子熔丝与触发网络电耦合并且被配置为使得ESD保护装置在吹动电熔丝之后对触发信号不敏感。

公开(公告)号：US20110001551A1

公开(公告)日：2011-01-06

申请号：US12496002

申请日：2009-07-01

申请人： Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, JR. ,  Christopher S. Putnam ,  Souvick Mitra

发明人： Michel J. Abou-Khalil ,  Tom C. Lee ,  Junjun Li ,  Robert J. Gauthier, JR. ,  Christopher S. Putnam ,  Souvick Mitra

IPC分类号： H01H37/76

CPC分类号： G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse has two short high atomic diffusion resistance conductor layers positioned on opposite sides and at a same end of a long low atomic diffusion resistance conductor layer. A voltage source is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces. The formation of such opens and/or shorts can be used to achieve different programming states. Other circuit structure embodiments incorporate e-fuses with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

摘要翻译： 公开了电子熔丝编程/重新编程电路的实施例。 在一个实施例中，电熔丝具有位于长低的原子扩散电阻较长的导体层的相对侧和同一端的两个短的高原子扩散电阻的导体层。 使用电压源来改变施加到端子的电压的极性和可选的电压的大小，以便控制长导体层内的电子的双向流动，从而在长导体上形成开路和/或短路 层 - 短导体层接口。 可以使用这种打开和/或短路的形成来实现不同的编程状态。 其他电路结构实施例包括具有附加导体层和附加端子的电子保险丝，以便允许甚至更多的编程状态。 还公开了相关联的电熔丝编程和重新编程方法的实施例。

公开(公告)号：US08642452B2

公开(公告)日：2014-02-04

申请号：US13012137

申请日：2011-01-24

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L21/36

CPC分类号： H01L27/0255 ,  G06F17/5022 ,  G06F17/5045 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/6609 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/861

摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.

公开(公告)号：US08445355B2

公开(公告)日：2013-05-21

申请号：US12969004

申请日：2010-12-15

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

IPC分类号： H01L21/20

CPC分类号： H01L28/82 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

摘要翻译： 金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。 布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。

公开(公告)号：US08421128B2

公开(公告)日：2013-04-16

申请号：US11960030

申请日：2007-12-19

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H01L23/62

CPC分类号： H01L23/34 ,  H01L21/743 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/3677 ,  H01L27/0255 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A heat generating component of a semiconductor device is located between two heavily doped semiconductor regions in a semiconductor substrate. The heat generating component may be a middle portion of a diode having a light doping, a lightly doped p-n junction between a cathode and anode of a silicon controlled rectifier, or a resistive portion of a doped semiconductor resistor. At least one thermally conductive via comprising a metal or a non-metallic conductive material is place directly on the heat generating component. Alternatively, a thin dielectric layer may be formed between the heat generating component and the at least one thermally conductive via. The at least one thermally conductive via may, or may not, be connected to a back-end-of-line metal wire, which may be connected to higher level of metal wiring or to a handle substrate through a buried insulator layer.

摘要翻译： 半导体器件的发热元件位于半导体衬底中的两个重掺杂半导体区之间。 发热部件可以是具有轻掺杂的二极管的中间部分，可控硅整流器的阴极和阳极之间的轻掺杂p-n结或掺杂半导体电阻器的电阻部分。 至少一个包含金属或非金属导电材料的导热通孔直接放置在发热部件上。 或者，可以在发热部件和至少一个导热通孔之间形成薄介电层。 至少一个导热通孔可以连接到或可以不连接到后端金属线，其可以通过掩埋绝缘体层连接到较高级别的金属布线或者与手柄基板连接。

公开(公告)号：US20120257317A1

公开(公告)日：2012-10-11

申请号：US13079946

申请日：2011-04-05

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC分类号： H02H9/04 ,  H05K13/00 ,  G06F17/50

CPC分类号： H02H9/046 ,  H01L27/0262 ,  H03K19/00361 ,  Y10T29/49002

摘要： RC-trigger circuits for a semiconductor controlled rectifier (SCR), methods of providing electrostatic discharge (ESD) protection, and design structures for a RC-trigger circuit. The RC-trigger circuit is coupled to an input/output (I/O) signal pad by an isolation diode and is coupled to a power supply voltage by a power supply diode. Under normal operating conditions, the isolation diode is reverse biased, isolating the RC-trigger circuit from the input/output (I/O) pad, and the power supply diode is forward biased so that the RC-trigger circuit is supplied with power. The isolation diode may become forward biased during ESD events while the chip is unpowered, causing the RC-trigger circuit to trigger an SCR configured protect the signal pad from ESD into a conductive state. The power supply diode may become reverse biased during the ESD event, which isolates the power supply rail from the ESD voltage pulse.

摘要翻译： 用于半导体可控整流器（SCR）的RC触发电路，提供静电放电（ESD）保护的方法以及用于RC触发电路的设计结构。 RC触发电路通过隔离二极管耦合到输入/输出（I / O）信号焊盘，并通过电源二极管耦合到电源电压。 在正常工作条件下，隔离二极管反向偏置，将RC触发电路与输入/输出（I / O）焊盘隔离，电源二极管正向偏置，使RC触发电路供电。 在ESD事件期间，隔离二极管可能会在芯片未上电时产生正向偏置，导致RC触发电路触发SCR配置，从而将信号焊盘从ESD保护到导通状态。 在ESD事件期间，电源二极管可能会反向偏置，从而将电源轨与ESD电压脉冲隔离。