公开(公告)号：US20230099856A1

公开(公告)日：2023-03-30

申请号：US17665749

申请日：2022-02-07

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Julius Kovats

IPC: H01L23/498 ,  H01L23/50 ,  H01L25/065

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

公开(公告)号：US20230055102A1

公开(公告)日：2023-02-23

申请号：US17889760

申请日：2022-08-17

Applicant: Microchip Technology Incorporated

Inventor： Bomy Chen ,  Justin Sato

IPC: H01L23/31 ,  H01L23/552 ,  H01L23/29 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: An electronic device includes an integrated circuit package including a die mounted on a die carrier, a mold structure at least partially encapsulating the mounted die, and a heat transfer chimney formed on the die. The heat transfer chimney extends at least partially through the mold structure to transfer heat away from the die. The heat transfer chimney is formed from a thermally conductive compound including thermally conductive nanoparticles.

公开(公告)号：US11545544B2

公开(公告)日：2023-01-03

申请号：US17155431

申请日：2021-01-22

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L49/02

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

公开(公告)号：US11043471B2

公开(公告)日：2021-06-22

申请号：US16540117

申请日：2019-08-14

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498

Abstract: A mixed-orientation multi-die (“MOMD”) integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base. MOMD packages may provide a reduced lateral footprint and increased die integration per unit area, as compared with conventional multi-die packages.

公开(公告)号：US12205910B2

公开(公告)日：2025-01-21

申请号：US18141621

申请日：2023-05-01

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Gerald Marsico ,  Julius Kovats

IPC: H01L21/60 ,  H01L23/00

Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

公开(公告)号：US12205885B2

公开(公告)日：2025-01-21

申请号：US18218197

申请日：2023-07-05

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/67 ,  H01L23/528 ,  H01L49/02

Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.

公开(公告)号：US11735516B2

公开(公告)日：2023-08-22

申请号：US17306019

申请日：2021-05-03

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L21/66 ,  H01L23/528 ,  H01L49/02 ,  H01L21/67

CPC classification number: H01L23/5223 ,  H01L21/67259 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/40

Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.

公开(公告)号：US11682641B2

公开(公告)日：2023-06-20

申请号：US17163645

申请日：2021-02-01

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Gerald Marsico ,  Julius Kovats

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L24/89 ,  H01L2224/0361 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/05639 ,  H01L2224/05724 ,  H01L2224/05839 ,  H01L2224/08225 ,  H01L2224/80895

Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

公开(公告)号：US11670583B2

公开(公告)日：2023-06-06

申请号：US17117288

申请日：2020-12-10

Applicant: Microchip Technology incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L23/532 ,  H01F27/32 ,  H01F27/28 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01F27/2823 ,  H01F27/32 ,  H01L23/5329 ,  H01L23/53223 ,  H01L23/53238 ,  H01L28/10

Abstract: A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.

公开(公告)号：US20220130753A1

公开(公告)日：2022-04-28

申请号：US17306019

申请日：2021-05-03

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/67 ,  H01L49/02 ,  H01L23/528

Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.