公开(公告)号：US20220199634A1

公开(公告)日：2022-06-23

申请号：US17693035

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy ,  Ashonita A. Chavan

IPC: H01L27/11509 ,  H01G4/008 ,  H01G4/06 ,  H01G4/40 ,  H01L49/02 ,  H01L27/11504 ,  G11C11/22 ,  H01L27/11507

Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220157837A1

公开(公告)日：2022-05-19

申请号：US17589310

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N, Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffrey B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/78 ,  H01L29/66 ,  H01L21/223 ,  H01L29/10

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US11315939B2

公开(公告)日：2022-04-26

申请号：US17131065

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy ,  Ashonita A. Chavan

IPC: H01L27/11509 ,  H01G4/008 ,  H01G4/06 ,  H01G4/40 ,  H01L49/02 ,  H01L27/11504 ,  G11C11/22 ,  H01L27/11507

Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220093617A1

公开(公告)日：2022-03-24

申请号：US17027046

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L29/78 ,  H01L21/223 ,  H01L27/11597 ,  H01L27/1159 ,  H01L29/10 ,  H01L29/66

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US20200328221A1

公开(公告)日：2020-10-15

申请号：US16909770

申请日：2020-06-23

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy ,  Ashonita A. Chavan

IPC: H01L27/11509 ,  H01L27/11507 ,  H01L27/11504 ,  H01G4/06 ,  G11C11/22 ,  H01G4/40 ,  H01G4/008 ,  H01L49/02

Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200243267A1

公开(公告)日：2020-07-30

申请号：US16852284

申请日：2020-04-17

Applicant: Micron Technology, Inc.

Inventor： Ashonita A. Chavan ,  Beth R. Cook ,  Manuj Nahar ,  Durai Vishak Nirmal Ramaswamy

IPC: H01G4/38 ,  H01L27/11507 ,  G11C11/22 ,  H01L49/02

Abstract: Some embodiments include an apparatus having horizontally-spaced bottom electrodes supported by a supporting structure. Leaker device material is directly against the bottom electrodes. Insulative material is over the bottom electrodes, and upper electrodes are over the insulative material. Plate material extends across the upper electrodes and couples the upper electrodes to one another. The plate material is directly against the leaker device material. The leaker device material electrically couples the bottom electrodes to the plate material, and may be configured to discharge at least a portion of excess charge from the bottom electrodes to the plate material. Some embodiments include methods of forming apparatuses which include capacitors having bottom electrodes and top electrodes, with the top electrodes being electrically coupled to one another through a conductive plate. Leaker devices are formed to electrically couple the bottom electrodes to the conductive plate.

公开(公告)号：US20200235111A1

公开(公告)日：2020-07-23

申请号：US16255569

申请日：2019-01-23

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy ,  Ashonita A. Chavan

IPC: H01L27/11509 ,  H01G4/008 ,  H01G4/06 ,  H01G4/40 ,  H01L27/11507 ,  H01L27/11504 ,  G11C11/22 ,  H01L49/02

Abstract: Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200075330A1

公开(公告)日：2020-03-05

申请号：US16122004

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy ,  Michael Mutch ,  Sameer Chhajed

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/786 ,  H01L27/12

Abstract: A method includes forming a first amorphous material, forming a second amorphous material over and in contact with the first material, removing a portion of the second material and the first material to form pillars, and exposing the materials to a temperature between a crystallization temperature of the first material and a crystallization temperature of the second material. The first material and the second material each comprise at least one element selected from the group consisting of silicon and germanium. The second material exhibits a crystallization temperature different than a crystallization temperature of the first material. Semiconductor structures, memory devices, and systems are also disclosed.

公开(公告)号：US20200020708A1

公开(公告)日：2020-01-16

申请号：US16582182

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507

Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally outward of the upper and lower capacitor electrode linings. Conductive material is formed laterally outward of the capacitor insulator to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Other methods and structure independent of method of manufacture are disclosed.

公开(公告)号：US10438643B2

公开(公告)日：2019-10-08

申请号：US16194820

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Steven C. Nicholes ,  Ashonita A. Chavan ,  Matthew N. Rocklein

IPC: G11C11/00 ,  G11C11/22 ,  H01L27/11502 ,  G11C14/00 ,  G11C11/56 ,  G11C13/04 ,  H01L27/11507 ,  H01L49/02

Abstract: Methods of operating a ferroelectric memory cell. The method includes applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell having a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. Another of the positive bias voltage and the negative bias voltage is applied to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Related ferroelectric memory cells include a ferroelectric material exhibiting asymmetric switching properties.