公开(公告)号：US11955203B2

公开(公告)日：2024-04-09

申请号：US17629600

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Jie Yang ,  Xu Zhang ,  Bin Zhao

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1084 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/14

Abstract: Methods, systems, and devices for mitigating memory die misalignment are described. A memory system may receive a command to write data to a memory device including a memory die. The memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. If the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. For example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. To mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.

公开(公告)号：US11954336B2

公开(公告)日：2024-04-09

申请号：US17637428

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Liu Yang ,  Xiaolai Zhu ,  Bin Zhao

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

公开(公告)号：US20250021245A1

公开(公告)日：2025-01-16

申请号：US18781613

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Lingyun Wang

IPC: G06F3/06 ,  G06F12/1009

Abstract: Methods, systems, and devices for read operations for active regions of a memory device are described. A memory system that includes a non-volatile memory device may receive a command to enter a first power mode. Before entering the first power mode, the memory system may store an indication of the active regions of the non-volatile memory device that are active for use as part of a host performance booster (HPB) mode. The memory device may receive an HPB command while in the first power mode, and may subsequently enter (e.g., re-enter) the second power mode. In some examples, the HPB command may be processed based on its physical address being included in one of the active regions of the non-volatile memory device.

公开(公告)号：US20240295971A1

公开(公告)日：2024-09-05

申请号：US18604118

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Xing Wang ,  Liu Yang ,  Xiaolai Zhu ,  Bin Zhao

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

公开(公告)号：US11868245B2

公开(公告)日：2024-01-09

申请号：US17272113

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Xinghui Duan ,  Bin Zhao ,  Jianxiong Huang

IPC: G06F12/02 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0623 ,  G06F13/1668 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Devices and techniques for improving memory access operations of a memory device are provided. In an example, a method can include loading multiple LBA-to-physical address (L2P) regions of an L2P table from memory arrays of the memory device to a mapping cache in response to determining the LBA of the memory access command is not within the L2P region including of a mapping cache. When the memory access command is a sequential command, the multiple L2P regions loaded to the mapping cache can provide improved memory access performance.

公开(公告)号：US20230359552A1

公开(公告)日：2023-11-09

申请号：US17633525

申请日：2021-03-18

Applicant: Micron Technology, Inc.

Inventor： Bin Zhao ,  Jonathan S. Parry ,  Deping He ,  Xu Zhang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices for memory write performance techniques are described. A memory system may receive a sequence of commands, for example from a host system. Based on a relationship between logical block addresses of the sequence of commands, the memory system may delay performing a memory management operation (e.g., a garbage collection procedure, a power operation, a cache synchronization operation, a data relocation operation, or the like) for a duration. For example, the memory system may determine whether a quantity of write commands in the sequence that include non-consecutive logical block addresses exceeds a threshold. In some cases, the memory system may perform one or more commands in the sequence during the duration. Subsequently (e.g., at the end of the duration), the memory system may perform the memory management operation.