公开(公告)号：US20230045463A1

公开(公告)日：2023-02-09

申请号：US17393727

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan

IPC: G06F3/06

Abstract: A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.

公开(公告)号：US20220188247A1

公开(公告)日：2022-06-16

申请号：US17117933

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

IPC: G06F13/16 ,  G06F1/26

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

公开(公告)号：US20250094364A1

公开(公告)日：2025-03-20

申请号：US18967215

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

IPC: G06F13/16 ,  G06F1/26

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

公开(公告)号：US20250045217A1

公开(公告)日：2025-02-06

申请号：US18924299

申请日：2024-10-23

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Chulbum Kim ,  Dustin J. Carter

IPC: G06F13/16 ,  G06F12/10 ,  G06F13/42 ,  G11C16/04 ,  H03M9/00

Abstract: A reference clock signal is received by an active input/output expander (AIOE), from a memory sub-system controller, via a first interface of the AIEO. A signal corresponding to data associated with an input/output (I/O) command is received from a memory device, via a second interface of the AIOE. The signal corresponding to the data is converted to a first interface-compliant signal based on the reference clock signal. The first interface-compliant signal is sent to the memory sub-system controller via the first interface.

公开(公告)号：US12169461B2

公开(公告)日：2024-12-17

申请号：US17963773

申请日：2022-10-11

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Mark A. Helm ,  Yoav Weinberg

IPC: G06F13/14 ,  G06F1/26 ,  G06F13/16

Abstract: Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

公开(公告)号：US12130755B2

公开(公告)日：2024-10-29

申请号：US17468264

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Chulbum Kim ,  Dustin J. Carter

IPC: G06F13/16 ,  G06F12/10 ,  G06F13/42 ,  G11C16/04 ,  H03M9/00

CPC classification number: G06F13/1668 ,  G06F12/10 ,  G06F13/4234 ,  G06F13/4282 ,  G11C16/0483 ,  H03M9/00

Abstract: An input/output (I/O) command referencing a logical address of a memory sub-system is received by an active input/output expander (AIOE). The I/O command is received from a memory sub-system controller via the AIOE. The AIOE identifies a physical block address corresponding to the logical block address. The AIOE identifies, among a plurality of memory devices, a memory device associated with the physical block address. The AIOE converts the I/O command received via the serial interface to a parallel interface compliant I/O command. The AIOE sends the parallel interface compliant I/O command to the memory device.

公开(公告)号：US20240069738A1

公开(公告)日：2024-02-29

申请号：US17898160

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan ,  Xiangyu Tang ,  Dustin J. Carter

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0679

Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

公开(公告)号：US20240069721A1

公开(公告)日：2024-02-29

申请号：US17823909

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Sundararajan Sankaranarayanan ,  Chulbum Kim ,  Xiangyu Tang

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0679

Abstract: Memory with switchable channels is disclosed herein. In one embodiment, a system comprises a controller, a plurality of memory dies, and a switch matrix. The switch matrix is coupled to the controller via two or more controller-side channels, and to the plurality of memory dies via a set of memory-side channels. The switch matrix is configured to selectively couple each controller-side channel of the two or more controller-side channels to each memory-side channel of the set of memory-side channels to provide dynamically configurable connections between the controller and one or more memory dies of the plurality of memory dies.

公开(公告)号：US11687237B2

公开(公告)日：2023-06-27

申请号：US17393727

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Sundararajan Sankaranarayanan

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A local media controller of a first memory device receives a first number of cycles broadcasted by a second memory device via a bus connecting the first memory device and the second memory device. The local media controller initializes a counter associated with the first memory device. Responsive to determining that the value of the counter matches the first number of cycles, the local media controller transmits a status of the first memory device via the bus. Furthermore, responsive to determining that the status is ready, the local media controller sends, to a memory sub-system controller managing the first memory device, a status of a memory region of the first memory device.

公开(公告)号：US20230063656A1

公开(公告)日：2023-03-02

申请号：US17591510

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Chulbum Kim ,  Brian Kwon ,  Erwin E. Yu ,  Kitae Park ,  Taehyun Kim

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/22 ,  G11C16/32 ,  G06F3/06

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.