公开(公告)号：US11600314B2

公开(公告)日：2023-03-07

申请号：US17201941

申请日：2021-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/406 ,  G11C11/408 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12

Abstract: Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not).

公开(公告)号：US20210279183A1

公开(公告)日：2021-09-09

申请号：US17329989

申请日：2021-05-25

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Sean S. Eilert ,  Bryce D. Cook

IPC: G06F12/14 ,  G06F12/02

Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

公开(公告)号：US20200159674A1

公开(公告)日：2020-05-21

申请号：US16192068

申请日：2018-11-15

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Sean S. Eilert ,  Bryce D. Cook

IPC: G06F12/14 ,  G06F12/02

Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

公开(公告)号：US20190304534A1

公开(公告)日：2019-10-03

申请号：US16444916

申请日：2019-06-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan

IPC: G11C11/406 ,  G11C7/04 ,  G11C11/4076

Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.

公开(公告)号：US20180190342A1

公开(公告)日：2018-07-05

申请号：US15910867

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  John D. Porter

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/408

Abstract: Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A refresh operation is then performed on at least one selected row of memory in the memory system based on the randomly-chosen seed row. Additional apparatuses and methods are described.

公开(公告)号：US20150318032A1

公开(公告)日：2015-11-05

申请号：US14800512

申请日：2015-07-15

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P. Wright

IPC: G11C7/22 ,  H03K19/00 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

Abstract translation: 描述了用于控制时钟树的时钟信号的装置，感测电路和方法。 一种示例性装置包括一个连续的写入命令检测电路，其被配置为响应于在写入命令寄存器的输出处提供的当前写入命令来检测在当前写入命令的连续写入命令周期内是否接收到下一个写入命令。 该示例设备还包括一个时钟信号控制电路，该时钟信号控制电路耦合到该连续的写命令检测电路，并且被配置为基于该连续的写入命令检测电路是否检测到下一个写入来控制到输入/输出（I / O） 命令在连续写入命令周期内。

公开(公告)号：US20250124964A1

公开(公告)日：2025-04-17

申请号：US18745068

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Donald M. Morgan

IPC: G11C11/406

Abstract: Apparatuses and methods per row activation counter testing (PRACT). A memory includes an aggressor detector circuit, which determines a row address to be an aggressor address after the row address is accessed a number of times. In a normal mode the address is an aggressor after a first number of activations, while in a PRACT mode the address is an aggressor after a second (generally lower) number of activations. For example, when the row is accessed a first value may be added to a count in the normal mode and a second (generally larger) value in the PRACT mode. When the count crosses a threshold, the row is an aggressor.

公开(公告)号：US20240231635A1

公开(公告)日：2024-07-11

申请号：US18405998

申请日：2024-01-05

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Bryan David Kerstetter

IPC: G06F3/06 ,  G06F21/56

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0679 ,  G06F21/566 ,  G06F2221/034

Abstract: A system for providing maximum row active time enforcement for memory devices is disclosed. A host device issues an activate command to activate a memory bank of a plurality of memory banks of a memory. The memory device activates the memory bank and determines whether a precharge command to close the first memory bank has been issued by the host device within a maximum threshold amount of time since issuance of the activate command. If the system determines that the precharge command has been issued by the host device within the threshold, the memory device closes the memory bank via the host-issued precharge command. If, however, the system determines that the precharge command has not been issued by the host device within the threshold, the memory device internally issues a precharge command to close the memory bank to reduce potential data loss and other harmful effects to the memory device.

公开(公告)号：US20240086319A1

公开(公告)日：2024-03-14

申请号：US17941592

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Alan J. Wilson ,  Bryan David Kerstetter

IPC: G06F12/02 ,  G11C29/10

CPC classification number: G06F12/0292 ,  G11C29/10 ,  G06F2212/1032 ,  G06F2212/657

Abstract: A memory device for extending addressable array space by incorporating virtual and physical memory arrays is disclosed. When extra storage space beyond a physical memory array is needed by a controller of the memory device, the storage space may be provided by extending the address space using a virtual array. The memory device incorporates the use of an extra row address bit to increase the addressable space, whereby the extra bit is utilized to address virtual rows in the virtual array. Spare or redundant physical memory elements utilized for memory repair may be programmed to a virtual address space for the virtual memory array. When a memory device operation is activated, the extra row address bit is set to high, and the virtual row address matches with a spare or redundant memory element, the virtual row in the virtual array space is activated for performance of the operation.

公开(公告)号：US20240071558A1

公开(公告)日：2024-02-29

申请号：US17823740

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Alan John Wilson ,  Donald M. Morgan ,  John David Porter

IPC: G11C29/00 ,  G11C29/54

CPC classification number: G11C29/76 ,  G11C29/54 ,  G11C29/808

Abstract: Apparatus and methods for page-based soft post package repair are disclosed. Based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. A match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. A decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. A page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.