公开(公告)号：US20240194630A1

公开(公告)日：2024-06-13

申请号：US18530896

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： See Hiong LEOW ,  Hong Wan NG ,  Seng Kim YE ,  Kelvin Aik Boo TAN ,  Ling PAN

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/48 ,  H01L21/4853 ,  H01L24/45 ,  H01L24/49 ,  H01L24/85 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48229 ,  H01L2224/49109 ,  H01L2224/85447 ,  H01L2224/85801

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. In some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. The semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. In some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.

公开(公告)号：US20240162206A1

公开(公告)日：2024-05-16

申请号：US18503560

申请日：2023-11-07

Applicant: Micron Technology, Inc.

Inventor： Seng Kim YE ,  Hong Wan NG ,  Kelvin Aik Boo TAN ,  See Hiong LEOW ,  Ling PAN

IPC: H01L25/16 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/16 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2924/0665

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. The semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. The load switch may include multiple second electrical contacts disposed on the second outer surface. The semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.

公开(公告)号：US20240128182A1

公开(公告)日：2024-04-18

申请号：US18047411

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Chin Hui CHONG ,  Seng Kim YE ,  Hong Wan NG ,  Kelvin Aik Boo TAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48228 ,  H01L2224/48229 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73257 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.