公开(公告)号：US10665307B2

公开(公告)日：2020-05-26

申请号：US16432059

申请日：2019-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/06 ,  G11C16/34 ,  G11C29/04 ,  G01R31/02 ,  G11C16/10 ,  G11C29/02 ,  G11C8/08 ,  G11C7/00 ,  G11C29/50 ,  G11C7/02 ,  G01R31/28 ,  G01R31/30 ,  G11C16/26 ,  G11C29/12 ,  G11C16/00

Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.

公开(公告)号：US09761322B2

公开(公告)日：2017-09-12

申请号：US15019397

申请日：2016-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffery A. Kessenich ,  Joemar Sinipete ,  Chiming Chu ,  Jason L. Nevill ,  Kenneth W. Marr ,  Renato C. Padilla

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C29/04 ,  G01R31/02 ,  G11C29/02 ,  G11C8/08 ,  G11C7/00 ,  G11C29/50 ,  G11C7/02 ,  G11C29/12

CPC classification number: G11C16/3459 ,  G01R31/02 ,  G11C7/00 ,  G11C7/02 ,  G11C8/08 ,  G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/02 ,  G11C29/025 ,  G11C29/04 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/5006

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.