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公开(公告)号：US11711987B2
公开(公告)日：2023-07-25
申请号：US17007156
申请日：2020-08-31
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Robert J. Gleixner
CPC classification number: H10N70/8265 , H10B63/00 , H10N70/063 , H10N70/841 , H10N70/8833
Abstract: The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.
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公开(公告)号：US20230014459A1
公开(公告)日：2023-01-19
申请号：US17953247
申请日：2022-09-26
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Robert J. Gleixner
Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
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公开(公告)号：US11455210B1
公开(公告)日：2022-09-27
申请号：US17239864
申请日：2021-04-26
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Robert J. Gleixner
Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
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公开(公告)号：US20240413842A1
公开(公告)日：2024-12-12
申请号：US18608627
申请日：2024-03-18
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Nevil Gajera , Mohammed Ebrahim Hargan
Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.
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公开(公告)号：US11962327B2
公开(公告)日：2024-04-16
申请号：US17896957
申请日：2022-08-26
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Nevil Gajera , Mohammed Ebrahim Hargan
CPC classification number: H03M13/154 , H03M13/1575 , H03M13/153 , H03M13/1545 , H03M13/373 , H03M13/3746
Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.
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Patent Agency Ranking
公开(公告)号：US11868211B2
公开(公告)日：2024-01-09
申请号：US17953247
申请日：2022-09-26
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Robert J. Gleixner
CPC classification number: G06F11/1076 , G11C13/003 , G11C13/004 , G11C13/0004 , H03M13/152 , G11C2213/15
Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
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公开(公告)号：US20230223961A1
公开(公告)日：2023-07-13
申请号：US17896994
申请日：2022-08-26
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Nevil Gajera , Mohammed Ebrahim Hargan
CPC classification number: H03M13/373 , H03M13/153 , H03M13/154 , H03M13/1545 , H03M13/1575 , H03M13/3746
Abstract: Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.
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公开(公告)号：US20230223960A1
公开(公告)日：2023-07-13
申请号：US17896957
申请日：2022-08-26
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Nevil Gajera , Mohammed Ebrahim Hargan
IPC: H03M13/37
CPC classification number: H03M13/373 , H03M13/3746
Abstract: Provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ECC) decoding on a received word read from the plurality of memory components. The ECC decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.
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公开(公告)号：US11367483B2
公开(公告)日：2022-06-21
申请号：US17089146
申请日：2020-11-04
Applicant: Micron Technology, Inc.
Inventor： Josephine T. Hamada , Mingdong Cui , Joseph M. McCrate , Karthik Sarpatwari , Jessica Chen
Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.
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公开(公告)号：US20210151107A1
公开(公告)日：2021-05-20
申请号：US17089146
申请日：2020-11-04
Applicant: Micron Technology, Inc.
Inventor： Josephine T. Hamada , Mingdong Cui , Joseph M. McCrate , Karthik Sarpatwari , Jessica Chen
Abstract: Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.
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