公开(公告)号：US20230044728A1

公开(公告)日：2023-02-09

申请号：US17968775

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L25/065 ,  H01L25/00

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate.

公开(公告)号：US20220285315A1

公开(公告)日：2022-09-08

申请号：US17190324

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L25/065 ,  H01L25/00

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate.

公开(公告)号：US20220271013A1

公开(公告)日：2022-08-25

申请号：US17741799

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Yeongbeom Ko ,  Youngik Kwon ,  Jong Sik Paek ,  Jungbae Lee

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

公开(公告)号：US20210375822A1

公开(公告)日：2021-12-02

申请号：US17401887

申请日：2021-08-13

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/498

Abstract: Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

公开(公告)号：US20210183811A1

公开(公告)日：2021-06-17

申请号：US16711849

申请日：2019-12-12

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/498

Abstract: Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.

公开(公告)号：US20250029878A1

公开(公告)日：2025-01-23

申请号：US18759091

申请日：2024-06-28

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/304 ,  H01L21/3065 ,  H01L23/498

Abstract: A method of separating a semiconductor device from another semiconductor device using singulation grooves on a substrate is provided. The method includes providing a substrate with an upper surface and a back; forming a first semiconductor device on a first location on the upper surface; forming a second semiconductor device on a second location on the upper surface, such that a gap exists between the second semiconductor device and the first semiconductor device; forming a singulation groove on the upper surface that runs through the gap between the first and second semiconductor devices; partially filling an interior of the singulation groove with a brittle dielectric filler to form an air gap in the interior of the groove, and grinding to remove excess material from the back of the substrate, such that the singulation groove cracks and a separation is formed between the first semiconductor device and the second semiconductor device.

公开(公告)号：US20240145422A1

公开(公告)日：2024-05-02

申请号：US17974435

申请日：2022-10-26

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee ,  Bong Woo Choi

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L24/16 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48147 ,  H01L2224/48249 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate having a plurality of contact pads disposed at a coupling surface. A semiconductor die is coupled with the substrate at the plurality of contact pads, and a liquid-repelling material resistant to wetting by an underfill material is disposed at the coupling surface of the substrate surrounding a periphery of the semiconductor die. The underfill material is disposed between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the liquid-repelling material. As a result, the expansion of the underfill material beyond the semiconductor die may be controlled.

公开(公告)号：US20240014083A1

公开(公告)日：2024-01-11

申请号：US18217827

申请日：2023-07-03

Applicant: Micron Technology, Inc.

Inventor： Hem P. Takiar ,  Raj K. Bansal ,  Jian Wei Lim ,  Li Wang ,  Jungbae Lee

IPC: H01L23/16 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L24/48 ,  H01L21/4803 ,  H01L24/16 ,  H01L2224/73265 ,  H01L2224/48145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2924/182 ,  H01L2225/06562 ,  H01L2225/06506 ,  H01L2224/48227 ,  H01L2225/0651

Abstract: A method of making a semiconductor device assembly is provided. The method comprises attaching a first semiconductor device to an upper surface of a substrate and disposing a stencil over the upper surface of the substrate. The stencil includes (i) an opening and (ii) a cavity in which the first semiconductor device is disposed. The method further comprises screen-printing an epoxy material into the opening and onto the upper surface of the substrate, removing the stencil, and planarizing an upper surface of the epoxy material to form an epoxy spacer.

公开(公告)号：US20220084971A1

公开(公告)日：2022-03-17

申请号：US17021364

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/00 ,  H01L23/31

Abstract: Embossed solder masks for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a package substrate includes the solder mask with non-planar features along a surface of the solder mask such that the area of the surface is increased. The non-planar features may correspond to concave recesses formed on the surface of the solder mask. Physical dimensions (e.g., widths, depths) and/or areal densities of the non-planar features of the embossed solder masks may vary based on local areas of the package substrate exclusive of conductive bumps. The non-planar features may be formed by pressing a mold having convex features against the surface of the solder mask. The solder mask may be heated while pressing the mold against the surface of the solder mask. In some embodiments, the mold includes regions lacking the convex features.

公开(公告)号：US20210391277A1

公开(公告)日：2021-12-16

申请号：US16897867

申请日：2020-06-10

Applicant: Micron Technology, Inc.

Inventor： Jungbae Lee

IPC: H01L23/552 ,  H01L21/56

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam.