公开(公告)号：US11217576B1

公开(公告)日：2022-01-04

申请号：US17023037

申请日：2020-09-16

Applicant: Micron Technology, Inc.

Inventor： Quang Nguyen ,  Christopher Glancey ,  Shams U Arifeen ,  Koustav Sinha

IPC: H05K1/00 ,  H05K1/18 ,  H05K7/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H05K1/02 ,  H05K3/34 ,  H05K3/00

Abstract: Various embodiments described herein provide for printed circuit boards with one or more spaces for embedding components, which can be used to implement a memory sub-system.

公开(公告)号：US20210272921A1

公开(公告)日：2021-09-02

申请号：US16804413

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Christopher Glancey ,  Koustav Sinha

IPC: H01L23/00

Abstract: A microelectronic component comprises a substrate having at least one bond pad on a surface thereof and a metal pillar structure on the at least one bond pad, the metal pillar structure comprising a metal pillar on the at least one bond pad and a solder material having a portion within a reservoir within the metal pillar and another portion protruding from an end of the metal pillar opposite the at least one bond pad. Methods for forming the metal pillar structures, metal pillar structures, assemblies and systems incorporating the metal pillar structures are also disclosed.

公开(公告)号：US20250079371A1

公开(公告)日：2025-03-06

申请号：US18954176

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： Christopher Glancey ,  Shams U. Arifeen ,  Koustav Sinha ,  Quang Nguyen

IPC: H01L23/00

Abstract: Semiconductor die assemblies with flexible interconnects, and associated methods and systems are disclosed. The semiconductor die assembly includes a package substrate and a semiconductor die attached to the package substrate through the flexible interconnects. The flexible interconnects include one or more rigid sections and one or more flexible sections, each of which is disposed next to the rigid sections. The flexible sections may include malleable materials with relatively low melting temperatures (e.g., having relatively low modulus at elevated temperatures) such that the flexible interconnects can have reduced flexural stiffness during the assembly process. The malleable materials of the flexible interconnects, through plastic deformation in response to stress generated during the assembly process, may facilitate portions of the flexible interconnects to shift so as to reduce transfer of the stress to other parts of the semiconductor die assembly-e.g., circuitry of the semiconductor die.

公开(公告)号：US12211814B2

公开(公告)日：2025-01-28

申请号：US18212665

申请日：2023-06-21

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Quang Nguyen ,  Christopher Glancey ,  Koustav Sinha ,  Chan H. Yoo

IPC: H01L23/00

Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

公开(公告)号：US20240407080A1

公开(公告)日：2024-12-05

申请号：US18652581

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： Quang Nguyen ,  Koustav Sinha ,  Christopher Glancey

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/00

Abstract: Systems, apparatuses, and methods related to a printed circuit board (PCB) with a plurality of layers are described. Embodiments of the present technology can include low coefficient of thermal expansion (CTE) strips, such as material with a CTE value of less than a threshold level, added into the core layer of the PCB. The added low CTE strips can lower the overall CTE mismatch between the PCB and the mounted components.

公开(公告)号：US11869862B2

公开(公告)日：2024-01-09

申请号：US17653610

申请日：2022-03-04

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Christopher Glancey ,  Koustav Sinha

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/1434

Abstract: A microelectronic component comprises a substrate having at least one bond pad on a surface thereof and a metal pillar structure on the at least one bond pad, the metal pillar structure comprising a metal pillar on the at least one bond pad and a solder material having a portion within a reservoir within the metal pillar and another portion protruding from an end of the metal pillar opposite the at least one bond pad. Methods for forming the metal pillar structures, metal pillar structures, assemblies and systems incorporating the metal pillar structures are also disclosed.

公开(公告)号：US11728307B2

公开(公告)日：2023-08-15

申请号：US17236499

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Quang Nguyen ,  Christopher Glancey ,  Koustav Sinha ,  Chan H. Yoo

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13078 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/3512

Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

公开(公告)号：US11646286B2

公开(公告)日：2023-05-09

申请号：US16719643

申请日：2019-12-18

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Christopher Glancey ,  Koustav Sinha ,  Xiao Li

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147

Abstract: Solder joints comprising two different solder materials having different melting points, an outer solder material extending over an inner solder material bonded to a conductive pad, the inner solder material having a lower melting point than a melting point of the outer solder material and being in a solid state at substantially ambient temperature. A metal material having a higher melting point than a melting point of either solder material may coat at least a portion of the inner solder material. Microelectronic components, assemblies and electronic systems incorporating the solder joints, as well as processes for forming and repairing the solder joints are also disclosed.

公开(公告)号：US20230061955A1

公开(公告)日：2023-03-02

申请号：US17591519

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Koustav Sinha ,  Quang Nguyen ,  Christopher Glancey ,  Shams U. Arifeen

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor package assembly includes a first mounting surface of a package substrate that faces a second mounting surface of a printed circuit board. A first structural element bond pad is mounted to the first mounting surface. A second structural element bond pad is mounted to the second mounting surface, and the first and second structural element bond pads are aligned with each other. A structural element is interconnected with a first solder joint to the first structural element bond pad and interconnected with a second solder joint to the second structural element bond pad. The structural element extends between the first and second structural element bond pads to absorb mechanical shock when a compressive force pushes one of the first and second mounting surfaces toward the other.

公开(公告)号：US20220077076A1

公开(公告)日：2022-03-10

申请号：US17013321

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Koustav Sinha ,  Shams U. Arifeen ,  Christopher Glancey

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor devices having reinforcement structures configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate can include a base structure and a reinforcement structure at least partially within a die shadow region of the substrate. The reinforcement structure can be at least partially surrounded by the base structure. The reinforcement structure has a higher stiffness than the base structure.