公开(公告)号：US12218079B2

公开(公告)日：2025-02-04

申请号：US18151029

申请日：2023-01-06

Applicant: Micron Technology, Inc.

Inventor： Koustav Sinha ,  Shams U. Arifeen ,  Christopher Glancey

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498

Abstract: Semiconductor devices having reinforcement structures configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate can include a base structure and a reinforcement structure at least partially within a die shadow region of the substrate. The reinforcement structure can be at least partially surrounded by the base structure. The reinforcement structure has a higher stiffness than the base structure.

公开(公告)号：US20220344295A1

公开(公告)日：2022-10-27

申请号：US17236499

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Quang Nguyen ,  Christopher Glancey ,  Koustav Sinha ,  Chan H. Yoo

IPC: H01L23/00

Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

公开(公告)号：US11348875B2

公开(公告)日：2022-05-31

申请号：US16803954

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Koustav Sinha ,  Xiaopeng Qu

IPC: H01L23/538 ,  H05K1/18 ,  H01L23/498 ,  H01L23/00

Abstract: Semiconductor devices having an array of flexible connectors configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector can include a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire can have a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration.

公开(公告)号：US20220028826A1

公开(公告)日：2022-01-27

申请号：US16937861

申请日：2020-07-24

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Christopher Glancey ,  Koustav Sinha

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/373

Abstract: Stacked semiconductor die assemblies with heat sinks and associated methods and systems are disclosed. In some embodiments, a controller carrying one or more memory dies may be attached to a front side of a substrate. The substrate may include a heat sink formed on its back side such that the heat sink can establish a thermal contact with the controller. Further, the heat sink may be coupled to a thermally conductive pad of a printed circuit board (PCB) that carries the substrate. In this manner, the controller may be provided with a heat path toward the PCB to dissipate thermal energy generated during operation. In some cases, the substrate may include a set of thermal vias extending from the heat sink toward the controller to enhance the thermal contact between the controller and the heat sink.

公开(公告)号：US11207744B2

公开(公告)日：2021-12-28

申请号：US16664627

申请日：2019-10-25

Applicant: Micron Technology, Inc.

Inventor： Koustav Sinha ,  Hyunsuk Chun

IPC: B23K1/20 ,  H01L23/498 ,  B23K101/40 ,  B23K101/42

Abstract: An apparatus for a BGA package includes a pad mounted on a substrate. The apparatus also includes a solder resist layer disposed over the substrate and a buffer layer disposed over the solder resist layer. The solder resist layer can have a first aperture and the buffer layer can have a second aperture. The first and second apertures are aligned such that at least a portion of the pad is exposed to create a solder-mask-defined mounting pad. A diameter of the second aperture is larger than a diameter of the first aperture.

公开(公告)号：US12211822B2

公开(公告)日：2025-01-28

申请号：US18372546

申请日：2023-09-25

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Christopher Glancey ,  Koustav Sinha

IPC: H01L23/367 ,  H01L23/373 ,  H01L25/065

Abstract: Stacked semiconductor die assemblies with heat sinks and associated methods and systems are disclosed. In some embodiments, a controller carrying one or more memory dies may be attached to a front side of a substrate. The substrate may include a heat sink formed on its back side such that the heat sink can establish a thermal contact with the controller. Further, the heat sink may be coupled to a thermally conductive pad of a printed circuit board (PCB) that carries the substrate. In this manner, the controller may be provided with a heat path toward the PCB to dissipate thermal energy generated during operation. In some cases, the substrate may include a set of thermal vias extending from the heat sink toward the controller to enhance the thermal contact between the controller and the heat sink.

公开(公告)号：US20240014171A1

公开(公告)日：2024-01-11

申请号：US18372546

申请日：2023-09-25

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Christopher Glancey ,  Koustav Sinha

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/373 ,  H01L2225/06562 ,  H01L2225/06589

Abstract: Stacked semiconductor die assemblies with heat sinks and associated methods and systems are disclosed. In some embodiments, a controller carrying one or more memory dies may be attached to a front side of a substrate. The substrate may include a heat sink formed on its back side such that the heat sink can establish a thermal contact with the controller. Further, the heat sink may be coupled to a thermally conductive pad of a printed circuit board (PCB) that carries the substrate. In this manner, the controller may be provided with a heat path toward the PCB to dissipate thermal energy generated during operation. In some cases, the substrate may include a set of thermal vias extending from the heat sink toward the controller to enhance the thermal contact between the controller and the heat sink.

公开(公告)号：US11769752B2

公开(公告)日：2023-09-26

申请号：US16937861

申请日：2020-07-24

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Christopher Glancey ,  Koustav Sinha

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/373

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/373 ,  H01L2225/06562 ,  H01L2225/06589

Abstract: Stacked semiconductor die assemblies with heat sinks and associated methods and systems are disclosed. In some embodiments, a controller carrying one or more memory dies may be attached to a front side of a substrate. The substrate may include a heat sink formed on its back side such that the heat sink can establish a thermal contact with the controller. Further, the heat sink may be coupled to a thermally conductive pad of a printed circuit board (PCB) that carries the substrate. In this manner, the controller may be provided with a heat path toward the PCB to dissipate thermal energy generated during operation. In some cases, the substrate may include a set of thermal vias extending from the heat sink toward the controller to enhance the thermal contact between the controller and the heat sink.

公开(公告)号：US20230260943A1

公开(公告)日：2023-08-17

申请号：US17674685

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Christopher Glancey ,  Shams U. Arifeen ,  Koustav Sinha ,  Quang Nguyen

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/13084 ,  H01L2224/13005 ,  H01L2224/0401 ,  H01L2224/13147 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/16227

Abstract: Semiconductor die assemblies with flexible interconnects, and associated methods and systems are disclosed. The semiconductor die assembly includes a package substrate and a semiconductor die attached to the package substrate through the flexible interconnects. The flexible interconnects include one or more rigid sections and one or more flexible sections, each of which is disposed next to the rigid sections. The flexible sections may include malleable materials with relatively low melting temperatures (e.g., having relatively low modulus at elevated temperatures) such that the flexible interconnects can have reduced flexural stiffness during the assembly process. The malleable materials of the flexible interconnects, through plastic deformation in response to stress generated during the assembly process, may facilitate portions of the flexible interconnects to shift so as to reduce transfer of the stress to other parts of the semiconductor die assembly—e.g., circuitry of the semiconductor die.

公开(公告)号：US11664360B2

公开(公告)日：2023-05-30

申请号：US17566397

申请日：2021-12-30

Applicant: Micron Technology, Inc.

Inventor： Quang Nguyen ,  Christopher Glancey ,  Shams U Arifeen ,  Koustav Sinha

IPC: H01L25/18 ,  H05K1/18 ,  H01L23/00 ,  H01L25/00 ,  H05K3/34 ,  H05K1/02 ,  H05K3/00

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L25/50 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/3436 ,  H01L2224/16225 ,  H01L2924/15153 ,  H05K3/0017 ,  H05K2201/10159

Abstract: Various embodiments described herein provide for printed circuit boards with one or more spaces for embedding components, which can be used to implement a memory sub-system.