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公开(公告)号:US12218079B2
公开(公告)日:2025-02-04
申请号:US18151029
申请日:2023-01-06
Applicant: Micron Technology, Inc.
Inventor: Koustav Sinha , Shams U. Arifeen , Christopher Glancey
IPC: H01L23/00 , H01L21/48 , H01L23/16 , H01L23/31 , H01L23/498
Abstract: Semiconductor devices having reinforcement structures configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate can include a base structure and a reinforcement structure at least partially within a die shadow region of the substrate. The reinforcement structure can be at least partially surrounded by the base structure. The reinforcement structure has a higher stiffness than the base structure.
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公开(公告)号:US20240292522A1
公开(公告)日:2024-08-29
申请号:US18424681
申请日:2024-01-26
Applicant: Micron Technology, Inc.
Inventor: Prasad Nagavenkata Nune , Christopher Glancey , Yeow Chon Ong , Hong Wan Ng
IPC: H05K1/02
CPC classification number: H05K1/0271 , H05K2201/09418 , H05K2201/10159
Abstract: A microelectronic device package assembly includes a package board and a stiffener device attached to the package board. The package board has a first side and a second side. The stiffener device includes an upper stiffener, a lower stiffener, and one or more damper device. The upper stiffener is above the first side of the package board and has a die side and a package side. The lower stiffener is interposed between the upper stiffener and the package board and has a damper side and a board side. The lower stiffener includes through-package anchors extending from the board side and through the package board. The one or more damper devices are interposed between and are in contact with each of the upper stiffener and the lower stiffener. Microelectronic devices and electronic systems are also described.
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公开(公告)号:US20240284590A1
公开(公告)日:2024-08-22
申请号:US18436892
申请日:2024-02-08
Applicant: Micron Technology, Inc.
Inventor: Chan H. Yoo , James M. Derderian , Walter L. Moden , Christopher Glancey
IPC: H05K1/02 , G01R31/309 , H05K3/28
CPC classification number: H05K1/0269 , G01R31/309 , H05K3/28
Abstract: Aspects of the present disclosure configure a processor to detect faults in a printed circuit board (PCB) solder mask using an optical waveguide. The processor directs an optical beam to an input of one or more optical waveguides embedded in a protective coating layer of a PCB, the protective coating layer being adjacent to one or more traces of the PCB. The processor measures a beam characteristic of the optical beam that is output by the one or more optical waveguides. The processor detects a disruption of the optical beam that is output by the one or more optical waveguides based on the beam characteristic. The processor detects a fault in the protective coating layer of the PCB based on detecting the disruption of the optical beam that is output by the one or more optical waveguides.
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4.
公开(公告)号:US20220344295A1
公开(公告)日:2022-10-27
申请号:US17236499
申请日:2021-04-21
Applicant: Micron Technology, Inc.
Inventor: Shams U. Arifeen , Quang Nguyen , Christopher Glancey , Koustav Sinha , Chan H. Yoo
IPC: H01L23/00
Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.
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5.
公开(公告)号:US20220028826A1
公开(公告)日:2022-01-27
申请号:US16937861
申请日:2020-07-24
Applicant: Micron Technology, Inc.
Inventor: Shams U. Arifeen , Christopher Glancey , Koustav Sinha
IPC: H01L25/065 , H01L23/367 , H01L23/373
Abstract: Stacked semiconductor die assemblies with heat sinks and associated methods and systems are disclosed. In some embodiments, a controller carrying one or more memory dies may be attached to a front side of a substrate. The substrate may include a heat sink formed on its back side such that the heat sink can establish a thermal contact with the controller. Further, the heat sink may be coupled to a thermally conductive pad of a printed circuit board (PCB) that carries the substrate. In this manner, the controller may be provided with a heat path toward the PCB to dissipate thermal energy generated during operation. In some cases, the substrate may include a set of thermal vias extending from the heat sink toward the controller to enhance the thermal contact between the controller and the heat sink.
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公开(公告)号:US20250014959A1
公开(公告)日:2025-01-09
申请号:US18737817
申请日:2024-06-07
Applicant: Micron Technology, Inc.
Inventor: Manish Nayini , Koustav Sinha , Christopher Glancey , Quang Nguyen
IPC: H01L23/31 , H01L21/56 , H01L23/00 , H01L23/498 , H01L25/10
Abstract: A microelectronic device includes a semiconductor die operatively coupled to a base structure. The device further includes an encapsulant substantially surrounding the semiconductor die. The device also includes one or more recesses vertically extending from an upper surface of the encapsulant to one or more locations at or proximate to an upper surface of the base structure.
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公开(公告)号:US20240117855A1
公开(公告)日:2024-04-11
申请号:US17962927
申请日:2022-10-10
Applicant: Micron Technology, Inc.
Inventor: Kaleb A. Wilson , Bradley R. Bitz , Mark A. Tverdy , Quang Nguyen , Christopher Glancey , Jagadeesh B. Ginjupalli , Pridhvi Dandu
CPC classification number: F16F15/04 , H05K5/0217 , F16F2226/04 , F16F2226/042
Abstract: Apparatuses, systems, and methods for a damper for a printed circuit board assembly (PCBA). One example apparatus can include a PCBA of a solid state drive (SSD) and a damper configured to contact the PCBA, contact an enclosure of the SSD, and damp shock impulses applied to the SSD.
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8.
公开(公告)号:US20230335522A1
公开(公告)日:2023-10-19
申请号:US18212665
申请日:2023-06-21
Applicant: Micron Technology, Inc.
Inventor: Shams U. Arifeen , Quang Nguyen , Christopher Glancey , Koustav Sinha , Chan H. Yoo
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/11 , H01L2224/1147 , H01L2224/13013 , H01L2224/13014 , H01L2224/13078 , H01L2224/13147 , H01L2224/13155 , H01L2924/3512
Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.
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公开(公告)号:US20230154868A1
公开(公告)日:2023-05-18
申请号:US18151029
申请日:2023-01-06
Applicant: Micron Technology, Inc.
Inventor: Koustav Sinha , Shams U. Arifeen , Christopher Glancey
IPC: H01L23/00 , H01L23/16 , H01L21/48 , H01L23/498 , H01L23/31
CPC classification number: H01L23/562 , H01L23/16 , H01L21/4853 , H01L23/49816 , H01L23/3128
Abstract: Semiconductor devices having reinforcement structures configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate can include a base structure and a reinforcement structure at least partially within a die shadow region of the substrate. The reinforcement structure can be at least partially surrounded by the base structure. The reinforcement structure has a higher stiffness than the base structure.
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公开(公告)号:US11552029B2
公开(公告)日:2023-01-10
申请号:US17013321
申请日:2020-09-04
Applicant: Micron Technology, Inc.
Inventor: Koustav Sinha , Shams U. Arifeen , Christopher Glancey
IPC: H01L23/00 , H01L23/16 , H01L21/48 , H01L23/498 , H01L23/31
Abstract: Semiconductor devices having reinforcement structures configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate can include a base structure and a reinforcement structure at least partially within a die shadow region of the substrate. The reinforcement structure can be at least partially surrounded by the base structure. The reinforcement structure has a higher stiffness than the base structure.
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