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    Memory cells, integrated structures and memory arrays
    11.
    发明授权
    Memory cells, integrated structures and memory arrays 有权

    公开(公告)号：US10727249B2

    公开(公告)日：2020-07-28

    申请号：US16410992

    申请日：2019-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Chris M. Carlson ,  M. Jared Barclay

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28

    Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

    Memory Cells, Integrated Structures and Memory Arrays
    12.
    发明申请
    Memory Cells, Integrated Structures and Memory Arrays 审中-公开

    公开(公告)号：US20180204849A1

    公开(公告)日：2018-07-19

    申请号：US15409412

    申请日：2017-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Chris M. Carlson ,  M. Jared Barclay

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792

    CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/518 ,  H01L29/7926

    Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    13.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20250037768A1

    公开(公告)日：2025-01-30

    申请号：US18919650

    申请日：2024-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  M. Jared Barclay ,  Andrew Li ,  Aireus Christensen

    IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.

    Memory arrays and methods used in forming a memory array
    16.
    发明授权
    Memory arrays and methods used in forming a memory array 有权

    公开(公告)号：US10756105B2

    公开(公告)日：2020-08-25

    申请号：US16200158

    申请日：2018-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Yoshiaki Fukuzumi ,  M. Jared Barclay ,  Emilio Camerlenghi ,  Paolo Tessariol

    IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/28

    Abstract: A method used in forming a memory array comprises forming a tier comprising conductor material above a substrate. Sacrificial islands comprising etch-stop material are formed directly above the conductor material of the tier comprising the conductor material. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the sacrificial islands and the tier comprising the conductor material. Etching is conducted through the insulative tiers and the wordline tiers to the etch-stop material of individual of the sacrificial islands to form channel openings that have individual bases comprising the etch-stop material. The sacrificial islands are removed through individual of the channel openings to extend the individual channel openings to the tier comprising the conductor material. Channel material is formed in the extended-channel openings to the tier comprising the conductor material. The channel material is electrically coupled with the conductor material of the tier comprising the conductor material. Structure independent of method is disclosed.

    Memory cells, integrated structures and memory arrays
    17.
    发明授权
    Memory cells, integrated structures and memory arrays 有权

    公开(公告)号：US10388667B2

    公开(公告)日：2019-08-20

    申请号：US16102987

    申请日：2018-08-14

    Applicant: Micron Technology, Inc.

    Inventor： Chris M. Carlson ,  M. Jared Barclay

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28

    Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

    Memory cells, integrated structures and memory arrays
    18.
    发明授权
    Memory cells, integrated structures and memory arrays 有权

    公开(公告)号：US10128265B2

    公开(公告)日：2018-11-13

    申请号：US15409412

    申请日：2017-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Chris Carlson ,  M. Jared Barclay

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792

    Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

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