公开(公告)号：US20240170027A1

公开(公告)日：2024-05-23

申请号：US18511479

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Hongyan LI ,  Marco REDAELLI

IPC: G11C5/14 ,  G06F1/26

CPC classification number: G11C5/147 ,  G06F1/263

Abstract: Implementations described herein relate to a power hold-off circuit and power hold-off circuit operation. In some implementations, a system may include a battery, a first pre-regulator that is connected to a first set components, a second pre-regulator that is connected to a second set of components, a second diode, and a power hold-off circuit. The power hold-off circuit may include a step-up regulator, a step-down regulator, one or more power hold-off capacitors, and a first diode. In some implementations, the second pre-regulator and the step-up regulator may be connected in parallel. In some other implementations, an output of the second pre-regulator may be connected to an input of the step-up regulator.

公开(公告)号：US20250140293A1

公开(公告)日：2025-05-01

申请号：US18834861

申请日：2022-11-17

Applicant: Micron Technology, Inc.

Inventor： Hongyan LI ,  Marco REDAELLI

IPC: G11C5/14 ,  G11C11/4074

Abstract: Implementations described herein relate to a power hold-off circuit and power hold-off circuit operation. In some implementations, a system may include a battery, and a power hold-off circuit. The power hold-off circuit may include a step-up regulator, a step-down regulator, a first abrupt power-loss (APL) switch, a second APL switch, and one or more power hold-off capacitors. The system may include a third APL switch between the battery and the power hold-off circuit. The third APL switch and the first APL switch may be in a closed state, and the second APL switch may be connected to the step-up regulator, when a voltage from the battery satisfies a voltage threshold. The third APL switch and the first APL switch may be in an open state, and the second APL switch may be connected to the step-down regulator, when the voltage from the battery does not satisfy the voltage threshold.

公开(公告)号：US20240338334A1

公开(公告)日：2024-10-10

申请号：US18621350

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Marco REDAELLI

IPC: G06F13/42 ,  G06F9/4401 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F9/4406 ,  G06F13/4063

Abstract: An embedded system includes a host device that includes a first peripheral component interconnect express (PCIe) interface; a non-volatile memory (NVM) device that includes a second PCIe interface; and a PCIe bus directly coupled to the first PCIe interface and the second PCIe interface for transmitting direct communications between the host device and the monolithic NVM device.

公开(公告)号：US20240231610A9

公开(公告)日：2024-07-11

申请号：US18048251

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Gaurav SINHA ,  Marco REDAELLI

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0631 ,  G06F3/0679

Abstract: Implementations described herein relate to a cluster namespace for a memory device. In some implementations, a memory device may receive a cluster namespace instruction, from a host device, that instructs the memory device to create a cluster namespace using memory resources of the memory device that are spread across a plurality of namespaces of the memory device. The memory device may identify namespace storage information that indicates memory resources associated with a plurality of namespaces of the memory device. The memory device may create the cluster namespace based on creating a plurality of extents that respectively map sets of logical block address ranges from the plurality of namespaces to the cluster namespace.

公开(公告)号：US20240170044A1

公开(公告)日：2024-05-23

申请号：US18511473

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Marco REDAELLI ,  Hongyan LI

IPC: G11C11/4074 ,  G11C5/14

CPC classification number: G11C11/4074 ,  G11C5/141 ,  G11C5/147

Abstract: Implementations described herein relate to a power hold-off circuit and power hold-off circuit operation. In some implementations, a system may include a battery, and a power hold-off circuit. The power hold-off circuit may include a step-up regulator, an abrupt power-loss (APL) switch, and one or more power hold-off capacitors. The APL switch may be connected to the battery when a voltage from the battery satisfies a voltage threshold. The APL switch may be connected to a step-down regulator or one or more power hold-off capacitors when the voltage from the battery does not satisfy the voltage threshold.

公开(公告)号：US20240168660A1

公开(公告)日：2024-05-23

申请号：US18511373

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Marco REDAELLI

IPC: G06F3/06 ,  G06F1/30

CPC classification number: G06F3/0625 ,  G06F1/30 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673

Abstract: Implementations described herein relate to abrupt power loss management. In some implementations, a memory device may receive a peripheral component interconnect express reset (PERST) signal. The memory device may perform a write protect operation based on receiving the PERST signal. The memory device may initiate a reduced power consumption state of the memory device based on a completion of the write protect operation.

公开(公告)号：US20240377974A1

公开(公告)日：2024-11-14

申请号：US18602370

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Marco REDAELLI ,  Gaurav SINHA

IPC: G06F3/06

Abstract: Implementations described herein relate to memory device initialization. In some implementations, a memory device may perform a first initialization for a first set of memory resources, the first initialization being associated with a boot image initialization. The memory device may enable a sideband interface, for data transfer between the memory device and a host device, based on a completion of the first initialization. The memory device may perform a second initialization for a second set of memory resources that is larger than the first set of memory resources. The memory device may enable a peripheral component interconnect express interface, for data transfer between the memory device and the host device, based on a completion of the second initialization.

公开(公告)号：US20240241823A1

公开(公告)日：2024-07-18

申请号：US18414355

申请日：2024-01-16

Applicant: Micron Technology, Inc.

Inventor： Gaurav SINHA ,  Marco REDAELLI

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Implementations described herein relate to a shared function for a multi-port memory device. In some implementations, a memory device may include a first port, a second port, and one or more components configured to manage a shared function of the memory device. The shared function of the memory device may enable a host device that is connected to the first port of the memory device to identify and enumerate the second port of the memory device. In some implementations, the shared function of the memory device may establish a virtual connection between the first port and the second port, and may enable the host device that is connected to the first port of the memory device to share a resource or a function with another host device that is connected to the second port of the memory device.

公开(公告)号：US20240184722A1

公开(公告)日：2024-06-06

申请号：US18521373

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Gaurav SINHA ,  Marco REDAELLI

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: Implementations described herein relate to a memory device that enables communication between multiple connected host devices. In some implementations, a memory device may receive, from a first host device in communication with the memory device, a send communication command instructing the memory device to transmit data from the first host device to at least a second host device in communication with the memory device. The memory device may receive, from the second host device, a receive communication command instructing the memory device to transmit data to the second host device from at least the first host device. The memory device may transmit a message from the first host device to the second host device based on the send communication command and the receive communication command.

公开(公告)号：US20240176548A1

公开(公告)日：2024-05-30

申请号：US18511484

申请日：2023-11-16

Applicant: Micron Technology, Inc.

Inventor： Marco REDAELLI ,  Steffen BUCH

IPC: G06F3/06 ,  G06F1/30

CPC classification number: G06F3/0659 ,  G06F1/30 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0673

Abstract: Implementations described herein relate to emergency data storing operation selection. In some implementations, a memory device may be configured to receive a peripheral component interconnect power loss notification (PLN) signal and a peripheral component interconnect express reset (PERST) signal. The memory device may be configured to determine whether to initiate a first data storing operation or a second data storing operation based on the PERST signal state based on a falling edge of the PLN signal. The memory device may be configured to selectively initiate the first data storing operation or the second data storing operation. The first data storing operation may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing operation may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss.