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    Memory device with a multi-mode communication mechanism
    11.
    发明授权
    Memory device with a multi-mode communication mechanism 有权

    公开(公告)号：US10805422B2

    公开(公告)日：2020-10-13

    申请号：US16540568

    申请日：2019-08-14

    Applicant: Micron Technology, Inc.

    Inventor： Matthew D. Rowley ,  Mark Bauer

    IPC: G06F12/02 ,  H04L29/08 ,  H04W88/06 ,  H04L29/06 ,  H04W88/16 ,  G06F13/16

    Abstract: A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

    Capacitive voltage divider for monitoring multiple memory components
    12.
    发明授权
    Capacitive voltage divider for monitoring multiple memory components 有权

    公开(公告)号：US10775424B2

    公开(公告)日：2020-09-15

    申请号：US16119640

    申请日：2018-08-31

    Applicant: Micron Technology, Inc.

    Inventor： Matthew D. Rowley

    IPC: G06F1/3225 ,  G01R27/26 ,  G06F1/3296 ,  G06F1/3234

    Abstract: A memory sub-system includes a plurality of memory components where at least two of the memory components are configured to operate at different supply voltages. A capacitive voltage divider (CVD) configured to, responsive to a status of use of each of the memory components, select between a plurality of connections of a plurality of capacitors to reduce an input voltage of the memory sub-system. The plurality of connections is configured to provide different voltage magnitudes that correspond to the different supply voltages, and the CVD is further configured to output the different supply voltages to enable the use of each of the memory components.

    POWER TRANSLATOR COMPONENT
    13.
    发明申请
    POWER TRANSLATOR COMPONENT 审中-公开

    公开(公告)号：US20200272218A1

    公开(公告)日：2020-08-27

    申请号：US16287162

    申请日：2019-02-27

    Applicant: Micron Technology, Inc.

    Inventor： Matthew D. Rowley

    IPC: G06F1/3234 ,  G06F1/26 ,  G11C16/30

    Abstract: An apparatus includes a power management integrated circuit (PMIC) and a power translator component coupled to the PMIC. The power translator component supplies power to the PMIC. The power translator component can further receive, from the PMIC, an indication that the PMIC has experienced a thermal event and responsive to receipt of the indication that the PMIC has experienced the thermal event, prevent powering of the PMIC.

    CAPACITIVE VOLTAGE MODIFIER FOR POWER MANAGEMENT
    14.
    发明申请
    CAPACITIVE VOLTAGE MODIFIER FOR POWER MANAGEMENT 审中-公开

    公开(公告)号：US20200090765A1

    公开(公告)日：2020-03-19

    申请号：US16684924

    申请日：2019-11-15

    Applicant: Micron Technology, Inc.

    Inventor： Matthew D. Rowley ,  Dustin J. Carter

    IPC: G11C16/30 ,  G11C5/14 ,  G06F1/26 ,  G05F1/46 ,  G06F1/28 ,  G01R19/165 ,  G11C16/10

    Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.

    Capacitive voltage dividers coupled to voltage regulators
    19.
    发明授权
    Capacitive voltage dividers coupled to voltage regulators 有权

    公开(公告)号：US11335384B2

    公开(公告)日：2022-05-17

    申请号：US17124582

    申请日：2020-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Matthew D. Rowley

    IPC: G11C5/14 ,  G06F1/30 ,  G06F1/3234 ,  G06F1/3296 ,  H02M1/00 ,  G06F1/26 ,  G06F1/28 ,  G05F1/46

    Abstract: A method of operating a memory sub-system includes receiving an input voltage at a power management (PM) component of a memory sub-system, where the PM component includes a capacitive voltage divider (CVD), a linear voltage regulator (LVR), and a switching voltage regulator (SVR). The method includes determining whether the input voltage corresponds to a low power mode of the memory sub-system and that the input voltage is higher than an uppermost supply voltage at which a memory component of the memory sub-system is configured to operate. The method further includes selectably coupling, responsive to a determination of the low power mode, the CVD and the LVR and sequentially reducing the input voltage by the CVD and the LVR to a supply voltage for the memory component, where the supply voltage is not higher than the uppermost supply voltage at which the memory component is configured to operate.

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